This paper deals with control-aware test architecture design for SOCs. The term test control refers to the control of mode of operation of all modules connected in different TAMs and the execution of the modules tests. We classify test control into two categories: (1) pseudo-static test control and (2) dynamic test control. Pseudo-static test control can be provided by means of a shift-register, where dynamic test control requires dedicated test pins. As the total number of chip pins available for test is limited, a large number of test control pins results in less TAM bandwidth available for test data. Therefore test architecture design should take the test control into account. To deal with pseudo-static test control for a given test architecture, we present two test strategies and discuss their impact on the corresponding test schedule. For dynamic test control, we present pin-constrained design of test architectures. Experimental results for the ITC'02 SOC test benchmarks show that the new pin-constrained design algorithm can save tip to 42 % in test time compared to the test times obtained from a conventional architecture design procedure.
|Title of host publication||The Eighth IEEE European Test Workshop, 2003. Proceedings|
|Publication status||Published - 2003|
|Event||8th IEEE European Test Workshop 2003 - Crowne Plaza Hotel, Maastricht, Netherlands|
Duration: 28 May 2003 → 28 May 2003
Conference number: 8
|Conference||8th IEEE European Test Workshop 2003|
|Period||28/05/03 → 28/05/03|