Construction and exploitation of VLIW ASIPs with multiple vector-widths

E. Diken; R. Jordans; L. Jozwiak; H. Corporaal

Construction and exploitation of VLIW ASIPs with multiple vector-widths

E. Diken, R. Jordans, L. Jozwiak, H. Corporaal

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

Many applications in important domains, such as communication, multimedia, etc. show a significant data-level parallelism (DLP). A large part of the DLP is usually exploited through application vectorization and implementation of vector operations in processors executing the applications. While the amount of DLP varies between applications of the same domain or even within a single application, processor architectures usually support a single vector width. This may not be optimal and may cause a substantial energy and performance inefficiency. Therefore, an adequate more sophisticated exploitation of DLP is highly relevant. This paper studies the construction and exploitation of VLIW ASIPs with multiple vector widths.

Original language	English
Title of host publication	Proceedings of the 3rd Mediterranean conference on Embedded Computing (MECO), 15-19 June 2014, Budva, Montenegro
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Publication status	Published - 2014
Event	3rd Mediterranean Conference on Embedded Computing, MECO 2014 - Budva, Montenegro Duration: 15 Jun 2014 → 19 Jun 2014 Conference number: 3

Conference

Conference	3rd Mediterranean Conference on Embedded Computing, MECO 2014
Abbreviated title	MECO 2014
Country/Territory	Montenegro
City	Budva
Period	15/06/14 → 19/06/14

Cite this

@inproceedings{6a1b357934f34d85ab2e7eabf22a8655,

title = "Construction and exploitation of VLIW ASIPs with multiple vector-widths",

abstract = "Many applications in important domains, such as communication, multimedia, etc. show a significant data-level parallelism (DLP). A large part of the DLP is usually exploited through application vectorization and implementation of vector operations in processors executing the applications. While the amount of DLP varies between applications of the same domain or even within a single application, processor architectures usually support a single vector width. This may not be optimal and may cause a substantial energy and performance inefficiency. Therefore, an adequate more sophisticated exploitation of DLP is highly relevant. This paper studies the construction and exploitation of VLIW ASIPs with multiple vector widths.",

author = "E. Diken and R. Jordans and L. Jozwiak and H. Corporaal",

year = "2014",

language = "English",

booktitle = "Proceedings of the 3rd Mediterranean conference on Embedded Computing (MECO), 15-19 June 2014, Budva, Montenegro",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "3rd Mediterranean Conference on Embedded Computing, MECO 2014, MECO 2014 ; Conference date: 15-06-2014 Through 19-06-2014",

}

Diken, E, Jordans, R, Jozwiak, L & Corporaal, H 2014, Construction and exploitation of VLIW ASIPs with multiple vector-widths. in Proceedings of the 3rd Mediterranean conference on Embedded Computing (MECO), 15-19 June 2014, Budva, Montenegro. Institute of Electrical and Electronics Engineers, Piscataway, 3rd Mediterranean Conference on Embedded Computing, MECO 2014, Budva, Montenegro, 15/06/14.

Construction and exploitation of VLIW ASIPs with multiple vector-widths. / Diken, E.; Jordans, R.; Jozwiak, L. et al.
Proceedings of the 3rd Mediterranean conference on Embedded Computing (MECO), 15-19 June 2014, Budva, Montenegro. Piscataway: Institute of Electrical and Electronics Engineers, 2014.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Construction and exploitation of VLIW ASIPs with multiple vector-widths

AU - Diken, E.

AU - Jordans, R.

AU - Jozwiak, L.

AU - Corporaal, H.

N1 - Conference code: 3

PY - 2014

Y1 - 2014

N2 - Many applications in important domains, such as communication, multimedia, etc. show a significant data-level parallelism (DLP). A large part of the DLP is usually exploited through application vectorization and implementation of vector operations in processors executing the applications. While the amount of DLP varies between applications of the same domain or even within a single application, processor architectures usually support a single vector width. This may not be optimal and may cause a substantial energy and performance inefficiency. Therefore, an adequate more sophisticated exploitation of DLP is highly relevant. This paper studies the construction and exploitation of VLIW ASIPs with multiple vector widths.

AB - Many applications in important domains, such as communication, multimedia, etc. show a significant data-level parallelism (DLP). A large part of the DLP is usually exploited through application vectorization and implementation of vector operations in processors executing the applications. While the amount of DLP varies between applications of the same domain or even within a single application, processor architectures usually support a single vector width. This may not be optimal and may cause a substantial energy and performance inefficiency. Therefore, an adequate more sophisticated exploitation of DLP is highly relevant. This paper studies the construction and exploitation of VLIW ASIPs with multiple vector widths.

M3 - Conference contribution

BT - Proceedings of the 3rd Mediterranean conference on Embedded Computing (MECO), 15-19 June 2014, Budva, Montenegro

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 3rd Mediterranean Conference on Embedded Computing, MECO 2014

Y2 - 15 June 2014 through 19 June 2014

ER -

Construction and exploitation of VLIW ASIPs with multiple vector-widths

Abstract

Conference

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