Abstract
Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor implies resource constraints. Instead of random-access registers, relative location storages or rotating register files are used to exploit the available parallelism of resources by means of reducing the initiation interval in pipelined schedules. Therefore, the compiler or synthesis tool must deal with the difficult tasks of scheduling of operations and location assignment of values while respecting all the constraints including the storage file capacity. This paper presents a method that handles constraints of relative location storages during scheduling together with timing and resource constraints. The characteristics of the coloring of conflict graphs, representing the relative overlap of value instances, are analyzed in order to identify the bottlenecks for location assignment with the aim of serializing their lifetimes. This is done with pairs of loop instances of values until it can be guaranteed that all constraints will be satisfied.
Original language | English |
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Title of host publication | IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 384-390 |
ISBN (Print) | 0-7803-7247-6 |
DOIs | |
Publication status | Published - 2001 |
Event | 2001 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) - San Jose, United States Duration: 4 Nov 2001 → 8 Nov 2001 |
Conference
Conference | 2001 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) |
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Country/Territory | United States |
City | San Jose |
Period | 4/11/01 → 8/11/01 |
Other | ICCAD |