Constraint analysis for DSP code generation

B. Mesman, A.H. Timmer, J. Meerbergen, van, J.A.G. Jess

Research output: Contribution to journalArticleAcademicpeer-review

13 Citations (Scopus)
144 Downloads (Pure)


Code generation methods for digital signal processing (DSP) applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms and resource constraints imposed by a hardware architecture. In this paper, we present a method for register binding and instruction scheduling based on the exploitation and analysis of the combination of resource and timing constraints. The analysis identifies implicit sequencing relations between operations in addition to the preceding constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing and resource constraints. The presented approach results in an efficient method to obtain high-quality instruction schedules with low register requirements
Original languageEnglish
Pages (from-to)44-57
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number1
Publication statusPublished - 1999


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