Congestion analysis and management

H.J.L. Westra

Research output: ThesisPhd Thesis 1 (Research TU/e / Graduation TU/e)

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Since the first integrated circuits in the late 1950s, the semiconductor industry has enjoyed exponential growth. This observation is illustrated by Moore’s law which states that the number of transistors that can be placed on an integrated circuit (chip) doubles roughly every two years. Other examples of approximately exponential behavior are the increase in clock speed at which digital circuits run and the decrease in size of features that can be printed by manufacturing equipment. Due to improvements in manufacturing technology, the performance of chips is increasingly determined by the lengths of the wires that connect the functional elements of a chip. These wires are realized (routed) very late in the design flow. Mismatch between routing resources and routing demand is known as congestion and can lead to detoured wires and too many vias. Such surprises usually have detrimental effect on performance and yield and should be avoided. In order to prevent routing problems later on, congestion needs to be considered at earlier stages of the design flow than is traditionally the case. Congestion maps display congestion hotspots, and are a means to communicate (potential) resource conflicts. In this thesis, two methods for fast estimation of such maps are proposed. The first uses a probabilistic approach, and the second is essentially a global router with focus on speed rather than overflow minimization. Using such methods, algorithms earlier in the design flow can take routing considerations into account without the need to actually invoke the routers, allowing for more effective and accurate decisions and optimizations. Many algorithms require that multi-pin connections are broken down into two-pin connections. This thesis introduces the concept of routing freedom for measuring the amount of flexibility in such connections and decompositions. In the face of uncertainty about what will happen later on in the design flow, it can be beneficial to create as much flexibility as possible. Unfortunately, more freedom also corresponds to more vias under certain conditions. This thesis demonstrates how freedom analysis can be used to optimize net decomposition using Steiner tree algorithms and improve global routing. During chip implementation there are typically multiple considerations. Important examples are congestion, vias and run time. Equivalently, (heuristic) algorithms may base decisions on several criteria. In this thesis, tiebreakers are used to deal with such situations instead of more traditional approaches based on weights. This approach is used extensively in a net decomposition algorithmand during global routing. The problems encountered in chip implementation are huge in size and complexity. Often, approaches without guarantee of optimality are therefore used, as is the case for many of the algorithms presented in this thesis. Such approaches need to be validated and compared by benchmarking. Therefore, an extensive software package implementing the ideas presented in this thesis has been developed. A large number of experiments have been conducted demonstrating the effectiveness and limitations of the proposed methods and the tradeoffs that need to be made.
Original languageEnglish
QualificationDoctor of Philosophy
Awarding Institution
  • Electrical Engineering
  • Groeneveld, P.R., Promotor
  • Otten, Ralph, Promotor
Award date24 Aug 2009
Place of PublicationEindhoven
Print ISBNs978-90-386-1921-7
Publication statusPublished - 2009


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