Concurrent L- and S-band class e-power amplifier in 65nm CMOS

R. Zhang; M. Acar; M. Apostolidou; M.P. Heijden, van der; D.M.W. Leenaerts

doi:10.1109/RFIC.2012.6242267

Concurrent L- and S-band class e-power amplifier in 65nm CMOS

R. Zhang, M. Acar, M. Apostolidou, M.P. Heijden, van der, D.M.W. Leenaerts

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

2 Downloads (Pure)

Abstract

A 65nm CMOS concurrent dual-band two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To implement sub-optimum class-E load impedance at L-band (1.0-1.3GHz) and S-band (2.8-3.1GHz), a concurrent transmission-line based dual-band output matching network is designed. The measurements show a drain efficiency (¿) >; 61% and a power-added efficiency (PAE) >; 50.5% for L-band (1.0-1.3GHz) with a output power Pout >; 30.4dBm. For S-band (2.8-3.1GHz) a ¿ >; 42.6% and a PAE >; 30% with a Pout >; 28.9dBm are achieved. The output power variations are within 0.8dB and 1.6dB, respectively.

Original language	English
Title of host publication	Proceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 17 - 19 June 2012, Montreal, Canada
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	217-220
DOIs	https://doi.org/10.1109/RFIC.2012.6242267
Publication status	Published - 2012

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Zhang, R., Acar, M., Apostolidou, M., Heijden, van der, M. P., & Leenaerts, D. M. W. (2012). Concurrent L- and S-band class e-power amplifier in 65nm CMOS. In Proceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 17 - 19 June 2012, Montreal, Canada (pp. 217-220). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/RFIC.2012.6242267

@inproceedings{931c18578d714360b52ffb37134337af,

title = "Concurrent L- and S-band class e-power amplifier in 65nm CMOS",

abstract = "A 65nm CMOS concurrent dual-band two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To implement sub-optimum class-E load impedance at L-band (1.0-1.3GHz) and S-band (2.8-3.1GHz), a concurrent transmission-line based dual-band output matching network is designed. The measurements show a drain efficiency (¿) >; 61% and a power-added efficiency (PAE) >; 50.5% for L-band (1.0-1.3GHz) with a output power Pout >; 30.4dBm. For S-band (2.8-3.1GHz) a ¿ >; 42.6% and a PAE >; 30% with a Pout >; 28.9dBm are achieved. The output power variations are within 0.8dB and 1.6dB, respectively.",

author = "R. Zhang and M. Acar and M. Apostolidou and {Heijden, van der}, M.P. and D.M.W. Leenaerts",

year = "2012",

doi = "10.1109/RFIC.2012.6242267",

language = "English",

pages = "217--220",

booktitle = "Proceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 17 - 19 June 2012, Montreal, Canada",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Zhang, R, Acar, M, Apostolidou, M, Heijden, van der, MP & Leenaerts, DMW 2012, Concurrent L- and S-band class e-power amplifier in 65nm CMOS. in Proceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 17 - 19 June 2012, Montreal, Canada. Institute of Electrical and Electronics Engineers, Piscataway, pp. 217-220. https://doi.org/10.1109/RFIC.2012.6242267

Concurrent L- and S-band class e-power amplifier in 65nm CMOS. / Zhang, R.; Acar, M.; Apostolidou, M. et al.
Proceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 17 - 19 June 2012, Montreal, Canada. Piscataway: Institute of Electrical and Electronics Engineers, 2012. p. 217-220.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Concurrent L- and S-band class e-power amplifier in 65nm CMOS

AU - Zhang, R.

AU - Acar, M.

AU - Apostolidou, M.

AU - Heijden, van der, M.P.

AU - Leenaerts, D.M.W.

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N2 - A 65nm CMOS concurrent dual-band two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To implement sub-optimum class-E load impedance at L-band (1.0-1.3GHz) and S-band (2.8-3.1GHz), a concurrent transmission-line based dual-band output matching network is designed. The measurements show a drain efficiency (¿) >; 61% and a power-added efficiency (PAE) >; 50.5% for L-band (1.0-1.3GHz) with a output power Pout >; 30.4dBm. For S-band (2.8-3.1GHz) a ¿ >; 42.6% and a PAE >; 30% with a Pout >; 28.9dBm are achieved. The output power variations are within 0.8dB and 1.6dB, respectively.

AB - A 65nm CMOS concurrent dual-band two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To implement sub-optimum class-E load impedance at L-band (1.0-1.3GHz) and S-band (2.8-3.1GHz), a concurrent transmission-line based dual-band output matching network is designed. The measurements show a drain efficiency (¿) >; 61% and a power-added efficiency (PAE) >; 50.5% for L-band (1.0-1.3GHz) with a output power Pout >; 30.4dBm. For S-band (2.8-3.1GHz) a ¿ >; 42.6% and a PAE >; 30% with a Pout >; 28.9dBm are achieved. The output power variations are within 0.8dB and 1.6dB, respectively.

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DO - 10.1109/RFIC.2012.6242267

M3 - Conference contribution

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BT - Proceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 17 - 19 June 2012, Montreal, Canada

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

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Concurrent L- and S-band class e-power amplifier in 65nm CMOS

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