A 65nm CMOS concurrent dual-band two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To implement sub-optimum class-E load impedance at L-band (1.0-1.3GHz) and S-band (2.8-3.1GHz), a concurrent transmission-line based dual-band output matching network is designed. The measurements show a drain efficiency (¿) >; 61% and a power-added efficiency (PAE) >; 50.5% for L-band (1.0-1.3GHz) with a output power Pout >; 30.4dBm. For S-band (2.8-3.1GHz) a ¿ >; 42.6% and a PAE >; 30% with a Pout >; 28.9dBm are achieved. The output power variations are within 0.8dB and 1.6dB, respectively.
|Title of host publication||Proceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 17 - 19 June 2012, Montreal, Canada|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2012|
Zhang, R., Acar, M., Apostolidou, M., Heijden, van der, M. P., & Leenaerts, D. M. W. (2012). Concurrent L- and S-band class e-power amplifier in 65nm CMOS. In Proceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 17 - 19 June 2012, Montreal, Canada (pp. 217-220). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/RFIC.2012.6242267