Abstract
| Language | English |
|---|---|
| Title of host publication | 2019 IEEE 15th International Conference on Automation Science and Engineering |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 486-493 |
| Number of pages | 8 |
| ISBN (Electronic) | 978-1-7281-0356-3 |
| DOIs | |
| State | Published - 2019 |
| Event | 15th IEEE International Conference on Automation Science and Engineering, (CASE 2019) - University of British Columbia, Vancouver, Canada Duration: 22 Aug 2019 → 26 Aug 2019 Conference number: 15 http://case2019.hust.edu.cn/ |
Conference
| Conference | 15th IEEE International Conference on Automation Science and Engineering, (CASE 2019) |
|---|---|
| Abbreviated title | CASE2019 |
| Country | Canada |
| City | Vancouver |
| Period | 22/08/19 → 26/08/19 |
| Internet address |
Fingerprint
Cite this
}
Computational effort of BDD-based supervisor synthesis of extended finite automata. / Thuijsman, Sander; Hendriks, D.; Theunissen, R.J.M.; Reniers, Michel; Schiffelers, Ramon.
2019 IEEE 15th International Conference on Automation Science and Engineering. Piscataway : Institute of Electrical and Electronics Engineers, 2019. p. 486-493.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - Computational effort of BDD-based supervisor synthesis of extended finite automata
AU - Thuijsman,Sander
AU - Hendriks,D.
AU - Theunissen,R.J.M.
AU - Reniers,Michel
AU - Schiffelers,Ramon
PY - 2019
Y1 - 2019
N2 - We consider supervisor synthesis of Extended Finite Automata that are represented using Binary Decision Diagrams (BDDs). Peak used BDD nodes and BDD operation count are introduced as platform independent and deterministic metrics that quantitatively indicate the computational effort needed to synthesize a supervisor. The use of BDD operation count is novel with respect to expressing supervisor synthesis effort. The (dis-)advantages of using these metrics to state of practice metrics such as wall clock time and worst case state space size are analyzed. The supervisor synthesis algorithm is initiated with a certain event- and variable order. It is already known from literature that variable order influences synthesis performance. We show that the event order is also relevant to consider. We discuss how these orders influence the synthesis effort and, by performing an experiment on a set of models, we show the extent of this influence.
AB - We consider supervisor synthesis of Extended Finite Automata that are represented using Binary Decision Diagrams (BDDs). Peak used BDD nodes and BDD operation count are introduced as platform independent and deterministic metrics that quantitatively indicate the computational effort needed to synthesize a supervisor. The use of BDD operation count is novel with respect to expressing supervisor synthesis effort. The (dis-)advantages of using these metrics to state of practice metrics such as wall clock time and worst case state space size are analyzed. The supervisor synthesis algorithm is initiated with a certain event- and variable order. It is already known from literature that variable order influences synthesis performance. We show that the event order is also relevant to consider. We discuss how these orders influence the synthesis effort and, by performing an experiment on a set of models, we show the extent of this influence.
U2 - 10.1109/COASE.2019.8843327
DO - 10.1109/COASE.2019.8843327
M3 - Conference contribution
SP - 486
EP - 493
BT - 2019 IEEE 15th International Conference on Automation Science and Engineering
PB - Institute of Electrical and Electronics Engineers
CY - Piscataway
ER -