Computational effort of BDD-based supervisor synthesis of extended finite automata

Sander Thuijsman, D. Hendriks, R.J.M. Theunissen, Michel Reniers, Ramon Schiffelers

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Abstract

We consider supervisor synthesis of Extended Finite Automata that are represented using Binary Decision Diagrams (BDDs). Peak used BDD nodes and BDD operation count are introduced as platform independent and deterministic metrics that quantitatively indicate the computational effort needed to synthesize a supervisor. The use of BDD operation count is novel with respect to expressing supervisor synthesis effort. The (dis-)advantages of using these metrics to state of practice metrics such as wall clock time and worst case state space size are analyzed. The supervisor synthesis algorithm is initiated with a certain event- and variable order. It is already known from literature that variable order influences synthesis performance. We show that the event order is also relevant to consider. We discuss how these orders influence the synthesis effort and, by performing an experiment on a set of models, we show the extent of this influence.
Original languageEnglish
Title of host publication2019 IEEE 15th International Conference on Automation Science and Engineering, CASE 2019
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages486-493
Number of pages8
ISBN (Electronic)978-1-7281-0356-3
DOIs
Publication statusPublished - Aug 2019
Event15th IEEE International Conference on Automation Science and Engineering, (CASE 2019) - University of British Columbia, Vancouver, Canada
Duration: 22 Aug 201926 Aug 2019
Conference number: 15
http://case2019.hust.edu.cn/

Conference

Conference15th IEEE International Conference on Automation Science and Engineering, (CASE 2019)
Abbreviated titleCASE2019
CountryCanada
CityVancouver
Period22/08/1926/08/19
Internet address

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