Composable virtual memory for an embedded SoC

C.H. Meenderinck, A.M. Molnos, K.G.W. Goossens

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)


Systems on a Chip concurrently execute multiple applications that may start and stop at run-time, creating many use-cases. Composability reduces the verifcation effort, by making the functional and temporal behaviours of an application independent of other applications. Existing approaches link applications to static address ranges that cannot be reused between applications that are not simultaneously active, wasting resources. In this paper we propose a composable virtual memory scheme that enables dynamic binding and relocation of applications. Our virtual memory is also predictable, for applications with real-time constraints. We integrated the virtual memory on, CompSOC, an existing composable SoC prototyped in FPGA. The implementation indicates that virtual memory is in general expensive, because it incurs a performance loss around 39% due to address translation latency. On top of this, composability adds to virtual memory an insigni cant extra performance penalty, below 1%.
Original languageEnglish
Title of host publicationProceedings of the 2012 15th Euromicro Conference on Digital System Design (DSD), 5-8 September 2012, Cesme, Izmir, Turkey
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Publication statusPublished - 2012
Event15th Euromicro Conference on Digital System Design (DSD 2012) - Çeşme, Turkey
Duration: 5 Sept 20128 Sept 2012
Conference number: 15


Conference15th Euromicro Conference on Digital System Design (DSD 2012)
Abbreviated titleDSD 2012
OtherConference co-located with the 38th Euromicro Conference on Software Engineering and Advanced Applications (SEAA 2012)
Internet address


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