Comparison of the implementation options of a summation function in high speed continuous-time sigma-delta ADCs

Analog-to-digital converters (ADCs) with large signal bandwidth (BW) and high resolution are needed for communication applications, e.g. base-station receivers. The continuous-time (CT) sigma-delta ADC [1] is a promising candidate for such applications because of its simple resistive input and inherent anti-aliasing filtering. In the design of high-speed CT sigma-delta ADC, the delay of the comparator and feedback DAC, which is referred to as excess loop delay (ELD), should be compensated with an extra high-speed feedback path [2]. A summation function of the ELD compensation feedback signal and the feed-forward signal from the loop filter’s output needs to be implemented. This poster will show a comparison between two possible circuit-level approaches for this summation function – current summation [3] and capacitive summation.
The purpose of this research is to compare both approaches mainly with respect to accuracy, power efficiency, and circuit complexity. To make a fair and quantitative comparison, an ideal register transfer level (RTL) 3rd-order 1bit CT sigma-delta ADC with several GSample/s sampling rate is synthesized and used as a common test bench. Both current and capacitive summation methods are implemented at transistor-level and optimized for the same resolution and signal bandwidth targets. Circuit-level non-idealities such as parasitic capacitance and mismatch are considered. The power consumption of both methods is analyzed and optimized for the same resolution target. Simulation results show that both methods can meet the resolution target, but for this speed and resolution current summation has a better power efficiency.