Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS

A. H. Montree, V. M.H. Meijssen, P. H. Woerlee

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

5 Citations (Scopus)

Abstract

A low voltage option in a 0.5 μm CMOS process technology is described. The key technological issue is the threshold voltage and sub-threshold leakage characteristics of the PMOS devices. The device properties of the n+-gate buried channel devices will be compared with the corresponding p+-gate surface channel devices. For power supply voltages down to 0.9 V the surface channel PMOS devices revealed superior transistor performance. Furthermore, the off-current characteristics are superior to the n+-gate buried channel devices. A minimum threshold voltage of -0.35 V of the 0.45 μm physical gate length PMOS transistor with less then 0.1 nA/μm leakage current was realised in a 0.5 μm CMOS process.

Original languageEnglish
Title of host publication1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers
Pages11-14
Number of pages4
ISBN (Print)0780309782
DOIs
Publication statusPublished - 1 Jan 1993
Externally publishedYes
Event1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Taipei, Taiwan
Duration: 12 May 199314 May 1993

Conference

Conference1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993
CountryTaiwan
CityTaipei
Period12/05/9314/05/93

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