Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS

A. H. Montree; V. M.H. Meijssen; P. H. Woerlee

doi:10.1109/VTSA.1993.263617

Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS

A. H. Montree, V. M.H. Meijssen, P. H. Woerlee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

A low voltage option in a 0.5 μm CMOS process technology is described. The key technological issue is the threshold voltage and sub-threshold leakage characteristics of the PMOS devices. The device properties of the n⁺-gate buried channel devices will be compared with the corresponding p⁺-gate surface channel devices. For power supply voltages down to 0.9 V the surface channel PMOS devices revealed superior transistor performance. Furthermore, the off-current characteristics are superior to the n⁺-gate buried channel devices. A minimum threshold voltage of -0.35 V of the 0.45 μm physical gate length PMOS transistor with less then 0.1 nA/μm leakage current was realised in a 0.5 μm CMOS process.

Original language	English
Title of host publication	1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers
Pages	11-14
Number of pages	4
ISBN (Print)	0780309782
DOIs	https://doi.org/10.1109/VTSA.1993.263617
Publication status	Published - 1 Jan 1993
Externally published	Yes
Event	1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Taipei, Taiwan Duration: 12 May 1993 → 14 May 1993

Conference

Conference	1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993
Country/Territory	Taiwan
City	Taipei
Period	12/05/93 → 14/05/93

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10.1109/VTSA.1993.263617

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Montree, A. H., Meijssen, V. M. H., & Woerlee, P. H. (1993). Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS. In 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers (pp. 11-14). [263617] Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VTSA.1993.263617

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title = "Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS",

abstract = "A low voltage option in a 0.5 μm CMOS process technology is described. The key technological issue is the threshold voltage and sub-threshold leakage characteristics of the PMOS devices. The device properties of the n+-gate buried channel devices will be compared with the corresponding p+-gate surface channel devices. For power supply voltages down to 0.9 V the surface channel PMOS devices revealed superior transistor performance. Furthermore, the off-current characteristics are superior to the n+-gate buried channel devices. A minimum threshold voltage of -0.35 V of the 0.45 μm physical gate length PMOS transistor with less then 0.1 nA/μm leakage current was realised in a 0.5 μm CMOS process.",

author = "Montree, {A. H.} and Meijssen, {V. M.H.} and Woerlee, {P. H.}",

year = "1993",

month = jan,

day = "1",

doi = "10.1109/VTSA.1993.263617",

language = "English",

isbn = "0780309782",

pages = "11--14",

booktitle = "1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 ; Conference date: 12-05-1993 Through 14-05-1993",

}

Montree, AH, Meijssen, VMH & Woerlee, PH 1993, Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS. in 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers., 263617, Institute of Electrical and Electronics Engineers, pp. 11-14, 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993, Taipei, Taiwan, 12/05/93. https://doi.org/10.1109/VTSA.1993.263617

Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS. / Montree, A. H.; Meijssen, V. M.H.; Woerlee, P. H.
1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers, 1993. p. 11-14 263617.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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N2 - A low voltage option in a 0.5 μm CMOS process technology is described. The key technological issue is the threshold voltage and sub-threshold leakage characteristics of the PMOS devices. The device properties of the n+-gate buried channel devices will be compared with the corresponding p+-gate surface channel devices. For power supply voltages down to 0.9 V the surface channel PMOS devices revealed superior transistor performance. Furthermore, the off-current characteristics are superior to the n+-gate buried channel devices. A minimum threshold voltage of -0.35 V of the 0.45 μm physical gate length PMOS transistor with less then 0.1 nA/μm leakage current was realised in a 0.5 μm CMOS process.

AB - A low voltage option in a 0.5 μm CMOS process technology is described. The key technological issue is the threshold voltage and sub-threshold leakage characteristics of the PMOS devices. The device properties of the n+-gate buried channel devices will be compared with the corresponding p+-gate surface channel devices. For power supply voltages down to 0.9 V the surface channel PMOS devices revealed superior transistor performance. Furthermore, the off-current characteristics are superior to the n+-gate buried channel devices. A minimum threshold voltage of -0.35 V of the 0.45 μm physical gate length PMOS transistor with less then 0.1 nA/μm leakage current was realised in a 0.5 μm CMOS process.

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M3 - Conference contribution

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BT - 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers

PB - Institute of Electrical and Electronics Engineers

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ER -

Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS

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