Comparison of an Æthereal network on chip and traditional interconnects: two case studies

A.J.M. Moonen, C.L.L. Bartels, M.J.G. Bekooij, R.M.J. Berg, van den, H. Bhullar, K.G.W. Goossens, P.R. Groeneveld, J. Huisken, J. Meerbergen, van

Research output: Chapter in Book/Report/Conference proceedingChapterAcademic

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The growing complexity of multiprocessor systems on chip make the integration of Intellectual Property (IP) blocks into a working system a major challenge. Networks-on-Chip (NoCs) facilitate a modular design approach which addresses the hardware challenges in designing such a system. Guaranteed communication services, offered by the Æthereal NoC, address the software challenges by making the system more robust and easier to design. This paper describes two existing bus-based reference designs and compares the original interconnects with an Æthereal NoC. We show through these two case study implementations that the area cost of the NoC, which is dominated by the number of network connections, is competitive with traditional interconnects. Furthermore, we show that the latency in the NoC-based design is still acceptable for our application.
Original languageEnglish
Title of host publicationVLSI-SoC: research trends in VLSI and systems on chip : Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2006), October 16 - 18, 2006, Nice, France
EditorsG. De Micheli, S. Mir, R. Reis
Place of PublicationBerlin
ISBN (Print)978-0-387-74908-2
Publication statusPublished - 2008

Publication series

NameIFIP International Federation for Information Processing
ISSN (Print)1571-5736


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