The growing complexity of multiprocessor systems on chip make the integration of Intellectual Property (IP) blocks into a working system a major challenge. Networks-on-Chip (NoCs) facilitate a modular design approach which addresses the hardware challenges in designing such a system. Guaranteed communication services, offered by the Æthereal NoC, address the software challenges by making the system more robust and easier to design. This paper describes two existing bus-based reference designs and compares the original interconnects with an Æthereal NoC. We show through these two case study implementations that the area cost of the NoC, which is dominated by the number of network connections, is competitive with traditional interconnects. Furthermore, we show that the latency in the NoC-based design is still acceptable for our application.
|Title of host publication||VLSI-SoC: research trends in VLSI and systems on chip : Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2006), October 16 - 18, 2006, Nice, France|
|Editors||G. De Micheli, S. Mir, R. Reis|
|Place of Publication||Berlin|
|Publication status||Published - 2008|
|Name||IFIP International Federation for Information Processing|
Moonen, A. J. M., Bartels, C. L. L., Bekooij, M. J. G., Berg, van den, R. M. J., Bhullar, H., Goossens, K. G. W., Groeneveld, P. R., Huisken, J., & Meerbergen, van, J. (2008). Comparison of an Æthereal network on chip and traditional interconnects: two case studies. In G. De Micheli, S. Mir, & R. Reis (Eds.), VLSI-SoC: research trends in VLSI and systems on chip : Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2006), October 16 - 18, 2006, Nice, France (pp. 317-336). (IFIP International Federation for Information Processing; Vol. 249). Springer. https://doi.org/10.1007/978-0-387-74909-9_18