We compare two standard techniques for satisfiability (SAT), which are basic for verification of microprocessor systems. We propose an approach for construction of shorter resolution refutations based on a standard approach called DPLL.
|Title of host publication||Proceedings International Conference on Mathematical Methods in Electromagnetic Theory, MMET '02, Kiev, Ukraine, September 10-13, 2002|
|Place of Publication||Piscataway NJ|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2002|