The design, simulation results and experimental characterization of a compact analog readout circuit for photon counting applications are presented in this paper. Two linear test arrays of 40 pixels with 25 μm pixel pitch have been fabricated in a 0.15 μm CMOS technology. Each pixel of the array consists of a Single-Photon Avalanche Diode (SPAD), a quenching circuit, a time-gating circuit and an analog counter. Each input pulse corresponding to a SPAD avalanche event is converted to a step in the output voltage. Along with compactness, the circuit was designed targeting low power consumption, good output linearity and sub-nanosecond timing resolution. The circuit features 8.6% pixel output nonuniformity and 1.1 % non-linearity. The gating circuit provides the sub-nanosecond window of 0.95 ns at FWHM. Consisting of a small number of transistors and occupying only 238μm2, this approach is suitable for the design of SPAD-based image sensors with high spatial resolution.