Compact CMOS analog counter for SPAD pixel arrays

In this brief, the design and experimental characterization of a compact analog readout circuit for photon counting is presented. A test chip, including a 20 × 20 counter array, has been manufactured in a standard 0.35- μm CMOS technology. The circuit delivers an output voltage proportional to the input pulse count, with a programmable voltage step. The counting resolution can be set to 7 or 8 bits with a readout noise of 0.15 and 0.3 electrons, respectively, and an output nonuniformity of 4% across the array, which brings a factor 3 improvement with respect to previous analog designs. A worst case integral nonlinearity of ±0.6 and ±1 LSB and a differential nonlinearity of ±0.3 and ±0.6 LSB were measured over the whole array of counters at 7- and 8-bit resolution, respectively. The area occupation of this analog implementation (230 μm²) is a factor 10 smaller than a digital counter of the same resolution. Due to the compactness and the lower counter power consumption with regard to the former designs, the proposed circuit can be exploited for signal processing in high-spatial resolution single-photon-avalanche-diode-based image sensors.