Abstract
| Original language | English |
|---|---|
| Title of host publication | 11th IEEE International Symposium on Industrial Embedded Systems (SIES), Krakow, Poland, 23-25 May 2016 |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 1-10 |
| Number of pages | 10 |
| ISBN (Electronic) | 978-1-5090-2282-3 |
| DOIs | |
| Publication status | Published - 2016 |
| Event | 11th IEEE International Symposium on Industrial Embedded Systems (SIES 2016), May 23-25, 2016, Krakow, Poland - Krakow, Poland Duration: 23 May 2016 → 25 May 2016 http://sies2016.org/ |
Conference
| Conference | 11th IEEE International Symposium on Industrial Embedded Systems (SIES 2016), May 23-25, 2016, Krakow, Poland |
|---|---|
| Abbreviated title | SIES 2016 |
| Country | Poland |
| City | Krakow |
| Period | 23/05/16 → 25/05/16 |
| Internet address |
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Communication aware multiprocessor binding for shared memory systems. / Adyanthaya, S.; Geilen, M.C.W.; Basten, T.; Voeten, J.P.M.; Schiffelers, R.R.H.
11th IEEE International Symposium on Industrial Embedded Systems (SIES), Krakow, Poland, 23-25 May 2016. Piscataway : Institute of Electrical and Electronics Engineers, 2016. p. 1-10.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - Communication aware multiprocessor binding for shared memory systems
AU - Adyanthaya, S.
AU - Geilen, M.C.W.
AU - Basten, T.
AU - Voeten, J.P.M.
AU - Schiffelers, R.R.H.
PY - 2016
Y1 - 2016
N2 - We present a three-step binding algorithm for applications in the form of directed acyclic graphs (DAGs) of tasks with deadlines, that need to be bound to a shared memory multiprocessor platform. The aim of the algorithm is to obtain a good binding that results in low makespans of the schedules of the DAGs. It first clusters tasks assuming unlimited resources using a deadline-aware shared memory extension of the existing dominant sequence clustering algorithm. Second, the clusters produced are merged based on communication dependencies to fit into the number of available platform resources. As a final step, the clusters are allocated to the available resources by balancing the workload. The approach is compared to the state of the art bounded dominant sequence clustering (BDSC) algorithm that also performs clustering on a limited number of resources. We show that our three-step algorithm makes better use of the shared memory communication structure and produces significantly lower makespans than BDSC on benchmark cases.
AB - We present a three-step binding algorithm for applications in the form of directed acyclic graphs (DAGs) of tasks with deadlines, that need to be bound to a shared memory multiprocessor platform. The aim of the algorithm is to obtain a good binding that results in low makespans of the schedules of the DAGs. It first clusters tasks assuming unlimited resources using a deadline-aware shared memory extension of the existing dominant sequence clustering algorithm. Second, the clusters produced are merged based on communication dependencies to fit into the number of available platform resources. As a final step, the clusters are allocated to the available resources by balancing the workload. The approach is compared to the state of the art bounded dominant sequence clustering (BDSC) algorithm that also performs clustering on a limited number of resources. We show that our three-step algorithm makes better use of the shared memory communication structure and produces significantly lower makespans than BDSC on benchmark cases.
U2 - 10.1109/SIES.2016.7509438
DO - 10.1109/SIES.2016.7509438
M3 - Conference contribution
SP - 1
EP - 10
BT - 11th IEEE International Symposium on Industrial Embedded Systems (SIES), Krakow, Poland, 23-25 May 2016
PB - Institute of Electrical and Electronics Engineers
CY - Piscataway
ER -