Communication aware multiprocessor binding for shared memory systems

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Abstract

We present a three-step binding algorithm for applications in the form of directed acyclic graphs (DAGs) of tasks with deadlines, that need to be bound to a shared memory multiprocessor platform. The aim of the algorithm is to obtain a good binding that results in low makespans of the schedules of the DAGs. It first clusters tasks assuming unlimited resources using a deadline-aware shared memory extension of the existing dominant sequence clustering algorithm. Second, the clusters produced are merged based on communication dependencies to fit into the number of available platform resources. As a final step, the clusters are allocated to the available resources by balancing the workload. The approach is compared to the state of the art bounded dominant sequence clustering (BDSC) algorithm that also performs clustering on a limited number of resources. We show that our three-step algorithm makes better use of the shared memory communication structure and produces significantly lower makespans than BDSC on benchmark cases.
Original languageEnglish
Title of host publication11th IEEE International Symposium on Industrial Embedded Systems (SIES), Krakow, Poland, 23-25 May 2016
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages1-10
Number of pages10
ISBN (Electronic)978-1-5090-2282-3
DOIs
Publication statusPublished - 2016
Event11th IEEE International Symposium on Industrial Embedded Systems (SIES 2016), May 23-25, 2016, Krakow, Poland - Krakow, Poland
Duration: 23 May 201625 May 2016
http://sies2016.org/

Conference

Conference11th IEEE International Symposium on Industrial Embedded Systems (SIES 2016), May 23-25, 2016, Krakow, Poland
Abbreviated titleSIES 2016
CountryPoland
CityKrakow
Period23/05/1625/05/16
Internet address

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