Co-design of a CMOS rectifier and small loop antenna for highly sensitive RF energy harvesters

M. Stoopman, S. Keyrouz, H.J. Visser, K.J.P. Philips, W.A. Serdijn

Research output: Contribution to journalArticleAcademicpeer-review

169 Citations (Scopus)
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Abstract

In this paper, a design method for the co-design and integration of a CMOS rectifier and small loop antenna is described. In order to improve the sensitivity, the antenna-rectifier interface is analyzed as it plays a crucial role in the co-design optimization. Subsequently, a 5-stage cross-connected differential rectifier with a 7-bit binary-weighted capacitor bank is designed and fabricated in standard 90 nm CMOS technology. The rectifier is brought at resonance with a high-Q loop antenna by means of a control loop that compensates for any variation at the antenna-rectifier interface and passively boosts the antenna voltage to enhance the sensitivity. A complementary MOS diode is proposed to improve the harvester's ability to store and hold energy over a long period of time during which there is insufficient power for rectification. The chip is ESD protected and integrated on a compact loop antenna. Measurements in an anechoic chamber at 868 MHz demonstrate a -27 dBm sensitivity for 1 V output across a capacitive load and 27 meter range for a 1.78 W RF source in an office corridor. The end-to-end power conversion efficiency equals 40% at -17 dBm.
Original languageEnglish
Pages (from-to)622-634
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Volume49
Issue number3
DOIs
Publication statusPublished - 2014

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