CMOS switched current phase-locked loop

D.M.W. Leenaerts; G.G. Persoon; B.M. Putter

doi:10.1049/ip-cds:19970907

CMOS switched current phase-locked loop

D.M.W. Leenaerts, G.G. Persoon, B.M. Putter

Research output: Contribution to journal › Article › Academic › peer-review

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Abstract

The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes

Original language	English
Pages (from-to)	75-77
Number of pages	3
Journal	IEE Proceedings - Circuits, Devices and Systems
Volume	144
DOIs	https://doi.org/10.1049/ip-cds:19970907
Publication status	Published - 1997

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title = "CMOS switched current phase-locked loop",

abstract = "The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes",

author = "D.M.W. Leenaerts and G.G. Persoon and B.M. Putter",

year = "1997",

doi = "10.1049/ip-cds:19970907",

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T1 - CMOS switched current phase-locked loop

AU - Leenaerts, D.M.W.

AU - Persoon, G.G.

AU - Putter, B.M.

PY - 1997

Y1 - 1997

N2 - The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes

AB - The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes

U2 - 10.1049/ip-cds:19970907

DO - 10.1049/ip-cds:19970907

M3 - Article

SN - 1350-2409

VL - 144

SP - 75

EP - 77

JO - IEE Proceedings - Circuits, Devices and Systems

JF - IEE Proceedings - Circuits, Devices and Systems

ER -

CMOS switched current phase-locked loop

Abstract

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