CMOS switched current phase-locked loop

D.M.W. Leenaerts, G.G. Persoon, B.M. Putter

Research output: Contribution to journalArticleAcademicpeer-review

4 Citations (Scopus)
101 Downloads (Pure)

Abstract

The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes
Original languageEnglish
Pages (from-to)75-77
Number of pages3
JournalIEE Proceedings - Circuits, Devices and Systems
Volume144
DOIs
Publication statusPublished - 1997

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