Clock buffer

V. Sharma (Inventor), R.I.M.P. Meijer (Inventor), J. Pineda de Gyvez (Inventor)

Research output: PatentPatent publication

20 Downloads (Pure)

Abstract

A tuneable buffer circuit for use in a clock tree has multiple buffers in parallel, each buffer having a grounding function, and also a bypass switch in parallel with the buffers. The circuit has a normal mode of one buffer connected into circuit, a first low voltage mode of multiple buffers connected into circuit in parallel without grounding function, a second low voltage mode of the buffers connected into circuit in parallel with grounding function and a bypass mode.

Original languageEnglish
Patent numberUS2014225645
IPCH03K 19/ 00 A I
Priority date12/02/13
Publication statusPublished - 14 Aug 2014

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