Abstract
A tuneable buffer circuit for use in a clock tree has multiple buffers in parallel, each buffer having a grounding function, and also a bypass switch in parallel with the buffers. The circuit has a normal mode of one buffer connected into circuit, a first low voltage mode of multiple buffers connected into circuit in parallel without grounding function, a second low voltage mode of the buffers connected into circuit in parallel with grounding function and a bypass mode.
Original language | English |
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Patent number | US2014225645 |
IPC | H03K 19/ 00 A I |
Priority date | 12/02/13 |
Publication status | Published - 14 Aug 2014 |