Circuit and method for comparator offset error detection and correction in ADC

P.J.A. Harpe (Inventor)

Research output: PatentPatent publication

Abstract

PROBLEM TO BE SOLVED: To provide a method for calibrating an analog-to-digital converter (ADC).SOLUTION: The method comprises: sampling an input voltage signal; comparing the sampled input voltage signal with an output signal of a feedback digital-to-analog converter (DAC) 40; determining in a search logic block 30 a digital code representation for a comparison result; and performing calibration by performing an additional cycle wherein the last comparison carried out for determining the least significant bit of the digital code representation is repeated with a second resolution mode different from a first resolution mode used in the last comparison, so obtaining an additional comparison, determining from the difference between the results of the additional comparison and the last comparison the sign of an offset error between the first and second resolution modes, and tuning, in accordance with the sign of the offset error, a programmable capacitor connected at input of a comparator 20, thereby inducing a voltage step to counteract the offset error.SELECTED DRAWING: Figure 2
Original languageEnglish
Patent numberUS 9537499 B2
Priority date19/02/15
Publication statusPublished - 3 Jan 2017

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Error detection
Error correction
Digital to analog conversion
Networks (circuits)
Electric potential
Capacitors
Tuning
Calibration
Sampling
Feedback

Cite this

@misc{e04d169d5b7f48049e5718c039dd8178,
title = "Circuit and method for comparator offset error detection and correction in ADC",
abstract = "PROBLEM TO BE SOLVED: To provide a method for calibrating an analog-to-digital converter (ADC).SOLUTION: The method comprises: sampling an input voltage signal; comparing the sampled input voltage signal with an output signal of a feedback digital-to-analog converter (DAC) 40; determining in a search logic block 30 a digital code representation for a comparison result; and performing calibration by performing an additional cycle wherein the last comparison carried out for determining the least significant bit of the digital code representation is repeated with a second resolution mode different from a first resolution mode used in the last comparison, so obtaining an additional comparison, determining from the difference between the results of the additional comparison and the last comparison the sign of an offset error between the first and second resolution modes, and tuning, in accordance with the sign of the offset error, a programmable capacitor connected at input of a comparator 20, thereby inducing a voltage step to counteract the offset error.SELECTED DRAWING: Figure 2",
author = "P.J.A. Harpe",
year = "2017",
month = "1",
day = "3",
language = "English",
type = "Patent",
note = "US 9537499 B2",

}

Circuit and method for comparator offset error detection and correction in ADC. / Harpe, P.J.A. (Inventor).

Patent No.: US 9537499 B2.

Research output: PatentPatent publication

TY - PAT

T1 - Circuit and method for comparator offset error detection and correction in ADC

AU - Harpe, P.J.A.

PY - 2017/1/3

Y1 - 2017/1/3

N2 - PROBLEM TO BE SOLVED: To provide a method for calibrating an analog-to-digital converter (ADC).SOLUTION: The method comprises: sampling an input voltage signal; comparing the sampled input voltage signal with an output signal of a feedback digital-to-analog converter (DAC) 40; determining in a search logic block 30 a digital code representation for a comparison result; and performing calibration by performing an additional cycle wherein the last comparison carried out for determining the least significant bit of the digital code representation is repeated with a second resolution mode different from a first resolution mode used in the last comparison, so obtaining an additional comparison, determining from the difference between the results of the additional comparison and the last comparison the sign of an offset error between the first and second resolution modes, and tuning, in accordance with the sign of the offset error, a programmable capacitor connected at input of a comparator 20, thereby inducing a voltage step to counteract the offset error.SELECTED DRAWING: Figure 2

AB - PROBLEM TO BE SOLVED: To provide a method for calibrating an analog-to-digital converter (ADC).SOLUTION: The method comprises: sampling an input voltage signal; comparing the sampled input voltage signal with an output signal of a feedback digital-to-analog converter (DAC) 40; determining in a search logic block 30 a digital code representation for a comparison result; and performing calibration by performing an additional cycle wherein the last comparison carried out for determining the least significant bit of the digital code representation is repeated with a second resolution mode different from a first resolution mode used in the last comparison, so obtaining an additional comparison, determining from the difference between the results of the additional comparison and the last comparison the sign of an offset error between the first and second resolution modes, and tuning, in accordance with the sign of the offset error, a programmable capacitor connected at input of a comparator 20, thereby inducing a voltage step to counteract the offset error.SELECTED DRAWING: Figure 2

UR - https://nl.espacenet.com/publicationDetails/originalDocument?CC=JP&NR=2016165103A&KC=A&FT=D&ND=3&date=20160908&DB=&locale=nl_NL#

M3 - Patent publication

M1 - US 9537499 B2

ER -