Chip scale 12-channel 10 Gb/s optical transmitter and receiver subassemblies based on wet etched silicon interposer

C. Li, T. Li, G. Guelbenzu de Villota, B. Smalbrugge, P. Stabile, O. Raz

Research output: Contribution to journalArticleAcademicpeer-review

21 Citations (Scopus)
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Abstract

In this paper, compact optical subassemblies are demonstrated based on a novel silicon interposer, which is designed and fabricated in a wafer scale process. The interposer includes the design of optical and electrical connections. A low-cost fabrication method, wet etching, is used to define light inputs and outputs as well as create the required recesses in the interposer to embed the chips into the silicon wafer at the same time. Impedance matched traces, for the high speed signals of the CMOS and opto-electronic ICs, are designed using advanced design system software and transferred onto the interposer by photolithography and electro-plating, which are accomplished on the deeply etched topology. The whole process flow of the silicon interposer patterning is designed and demonstrated, and the challenges are discussed. After the process, the optoelectronic dies and their complimentary CMOS parts are flipped and bonded on the interposer in close proximity, and a mechanical optical interface (MOI) is mounted for light coupling. Both transmitter and receiver subassemblies provide 12 parallel optical interconnections, and are scaled down to an area measuring 6 by 8 mm. Signal integrity testing is performed on a probe station for 10 Gb/s data signal delivering clear eye patterns for all channels (in both Rx and Tx subassemblies). The performance is further characterized using bit error rate (BER) testing. Both transmitter and receiver assemblies outperform a reference SFP+, with receiver sensitivity of-10 dBm at a BER lower than 10-12 after compensating for the MOI insertion loss. Finally, we also test the assemblies for crosstalk and demonstrate that the current design has a maximal additional penalty lower than 0.2 and 0.8 dB for transmitter and receiver, respectively.

Original languageEnglish
Article number7875398
Pages (from-to)3229-3236
Number of pages8
JournalJournal of Lightwave Technology
Volume35
Issue number15
DOIs
Publication statusPublished - 1 Aug 2017

Fingerprint

subassemblies
transmitters
receivers
chips
silicon
bit error rate
assemblies
CMOS
wafers
recesses
photolithography
crosstalk
penalties
plating
insertion loss
systems engineering
integrity
proximity
topology
stations

Keywords

  • Optical interconnections
  • optical transceiver
  • silicon interposer

Cite this

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title = "Chip scale 12-channel 10 Gb/s optical transmitter and receiver subassemblies based on wet etched silicon interposer",
abstract = "In this paper, compact optical subassemblies are demonstrated based on a novel silicon interposer, which is designed and fabricated in a wafer scale process. The interposer includes the design of optical and electrical connections. A low-cost fabrication method, wet etching, is used to define light inputs and outputs as well as create the required recesses in the interposer to embed the chips into the silicon wafer at the same time. Impedance matched traces, for the high speed signals of the CMOS and opto-electronic ICs, are designed using advanced design system software and transferred onto the interposer by photolithography and electro-plating, which are accomplished on the deeply etched topology. The whole process flow of the silicon interposer patterning is designed and demonstrated, and the challenges are discussed. After the process, the optoelectronic dies and their complimentary CMOS parts are flipped and bonded on the interposer in close proximity, and a mechanical optical interface (MOI) is mounted for light coupling. Both transmitter and receiver subassemblies provide 12 parallel optical interconnections, and are scaled down to an area measuring 6 by 8 mm. Signal integrity testing is performed on a probe station for 10 Gb/s data signal delivering clear eye patterns for all channels (in both Rx and Tx subassemblies). The performance is further characterized using bit error rate (BER) testing. Both transmitter and receiver assemblies outperform a reference SFP+, with receiver sensitivity of-10 dBm at a BER lower than 10-12 after compensating for the MOI insertion loss. Finally, we also test the assemblies for crosstalk and demonstrate that the current design has a maximal additional penalty lower than 0.2 and 0.8 dB for transmitter and receiver, respectively.",
keywords = "Optical interconnections, optical transceiver, silicon interposer",
author = "C. Li and T. Li and {Guelbenzu de Villota}, G. and B. Smalbrugge and P. Stabile and O. Raz",
year = "2017",
month = "8",
day = "1",
doi = "10.1109/JLT.2017.2681043",
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Chip scale 12-channel 10 Gb/s optical transmitter and receiver subassemblies based on wet etched silicon interposer. / Li, C.; Li, T.; Guelbenzu de Villota, G.; Smalbrugge, B.; Stabile, P.; Raz, O.

In: Journal of Lightwave Technology, Vol. 35, No. 15, 7875398, 01.08.2017, p. 3229-3236.

Research output: Contribution to journalArticleAcademicpeer-review

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T1 - Chip scale 12-channel 10 Gb/s optical transmitter and receiver subassemblies based on wet etched silicon interposer

AU - Li, C.

AU - Li, T.

AU - Guelbenzu de Villota, G.

AU - Smalbrugge, B.

AU - Stabile, P.

AU - Raz, O.

PY - 2017/8/1

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N2 - In this paper, compact optical subassemblies are demonstrated based on a novel silicon interposer, which is designed and fabricated in a wafer scale process. The interposer includes the design of optical and electrical connections. A low-cost fabrication method, wet etching, is used to define light inputs and outputs as well as create the required recesses in the interposer to embed the chips into the silicon wafer at the same time. Impedance matched traces, for the high speed signals of the CMOS and opto-electronic ICs, are designed using advanced design system software and transferred onto the interposer by photolithography and electro-plating, which are accomplished on the deeply etched topology. The whole process flow of the silicon interposer patterning is designed and demonstrated, and the challenges are discussed. After the process, the optoelectronic dies and their complimentary CMOS parts are flipped and bonded on the interposer in close proximity, and a mechanical optical interface (MOI) is mounted for light coupling. Both transmitter and receiver subassemblies provide 12 parallel optical interconnections, and are scaled down to an area measuring 6 by 8 mm. Signal integrity testing is performed on a probe station for 10 Gb/s data signal delivering clear eye patterns for all channels (in both Rx and Tx subassemblies). The performance is further characterized using bit error rate (BER) testing. Both transmitter and receiver assemblies outperform a reference SFP+, with receiver sensitivity of-10 dBm at a BER lower than 10-12 after compensating for the MOI insertion loss. Finally, we also test the assemblies for crosstalk and demonstrate that the current design has a maximal additional penalty lower than 0.2 and 0.8 dB for transmitter and receiver, respectively.

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