Checking pipelined disributed global properties for post-silicon debug

E. Larsson, H.G.H. Vermeulen, K.G.W. Goossens

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While multi-processor system-on-chips (MPSOCs) with network-on-chip (NOC) interconnect are becoming increasingly common to meet the constant performance demand, it is due to communication delays in the NOC extremely complicated to ensure that software executes correctly. In this paper, we extend our architecture that non-intrusively observes global properties at run time using distributed monitors such that not only single tokens but also pipelined tokens can be monitored. We detail the solution for a given race and compare the alternatives of having one large monitor versus multiple small monitors.
Original languageEnglish
Title of host publicationProceedings of the IEEE Eleventh Workshop on RTL and High Level Testing (WRTLT'10), 5-6 December 2010, Shanghai, China
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Publication statusPublished - 2010


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