Chaotic generation of PN sequences : a VLSI implementation

A. Dornbusch; J. Pineda de Gyvez

doi:10.1109/ISCAS.1999.777607

Chaotic generation of PN sequences : a VLSI implementation

A. Dornbusch
, J. Pineda de Gyvez

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

Generation of repeatable pseudo-random sequences with chaotic analog electronics is not feasible using standard circuit topologies. Component variation caused by imperfect fabrication causes the same divergence of output sequences as does varying initial conditions. By quantizing the output of a simple chaotic difference equation and using delayed feedback, we are able to construct a circuit which has properties both of randomness and repeatability. Simulation results show sequence lengths in excess of 10000 bits with cross correlations less than 0.02 for our architecture. The system has been implemented using AMI 1.2 µm CMOS technology, and digitally using AMD MACH complex programmable logic devices (CPLDs). Circuit measurements are in agreement with our theoretical findings

Original language	English
Title of host publication	Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999, ISCAS '99, 30 May - 2 June 1999, Orlando, Florida
Place of Publication	New York
Publisher	Institute of Electrical and Electronics Engineers
Pages	454-457
Volume	5
ISBN (Print)	0-7803-5471-0
DOIs	https://doi.org/10.1109/ISCAS.1999.777607
Publication status	Published - 1999
Externally published	Yes

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title = "Chaotic generation of PN sequences : a VLSI implementation",

abstract = "Generation of repeatable pseudo-random sequences with chaotic analog electronics is not feasible using standard circuit topologies. Component variation caused by imperfect fabrication causes the same divergence of output sequences as does varying initial conditions. By quantizing the output of a simple chaotic difference equation and using delayed feedback, we are able to construct a circuit which has properties both of randomness and repeatability. Simulation results show sequence lengths in excess of 10000 bits with cross correlations less than 0.02 for our architecture. The system has been implemented using AMI 1.2 µm CMOS technology, and digitally using AMD MACH complex programmable logic devices (CPLDs). Circuit measurements are in agreement with our theoretical findings",

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Chaotic generation of PN sequences : a VLSI implementation. / Dornbusch, A.; Pineda de Gyvez, J.
Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999, ISCAS '99, 30 May - 2 June 1999, Orlando, Florida. Vol. 5 New York: Institute of Electrical and Electronics Engineers, 1999. p. 454-457.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Chaotic generation of PN sequences : a VLSI implementation

AU - Dornbusch, A.

AU - Pineda de Gyvez, J.

PY - 1999

Y1 - 1999

N2 - Generation of repeatable pseudo-random sequences with chaotic analog electronics is not feasible using standard circuit topologies. Component variation caused by imperfect fabrication causes the same divergence of output sequences as does varying initial conditions. By quantizing the output of a simple chaotic difference equation and using delayed feedback, we are able to construct a circuit which has properties both of randomness and repeatability. Simulation results show sequence lengths in excess of 10000 bits with cross correlations less than 0.02 for our architecture. The system has been implemented using AMI 1.2 µm CMOS technology, and digitally using AMD MACH complex programmable logic devices (CPLDs). Circuit measurements are in agreement with our theoretical findings

AB - Generation of repeatable pseudo-random sequences with chaotic analog electronics is not feasible using standard circuit topologies. Component variation caused by imperfect fabrication causes the same divergence of output sequences as does varying initial conditions. By quantizing the output of a simple chaotic difference equation and using delayed feedback, we are able to construct a circuit which has properties both of randomness and repeatability. Simulation results show sequence lengths in excess of 10000 bits with cross correlations less than 0.02 for our architecture. The system has been implemented using AMI 1.2 µm CMOS technology, and digitally using AMD MACH complex programmable logic devices (CPLDs). Circuit measurements are in agreement with our theoretical findings

U2 - 10.1109/ISCAS.1999.777607

DO - 10.1109/ISCAS.1999.777607

M3 - Conference contribution

SN - 0-7803-5471-0

VL - 5

SP - 454

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BT - Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999, ISCAS '99, 30 May - 2 June 1999, Orlando, Florida

PB - Institute of Electrical and Electronics Engineers

CY - New York

ER -

Chaotic generation of PN sequences : a VLSI implementation

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