Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation

Y. V. Ponomarev; P. A. Stolk; A. C.M.C. van Brandenburg; R. Roes; A. H. Montree; J. Schmitz; P. H. Woerlee

doi:10.1109/IEDM.1998.746438

Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation

Y. V. Ponomarev
, P. A. Stolk
, A. C.M.C. van Brandenburg
, R. Roes
, A. H. Montree
, J. Schmitz
, P. H. Woerlee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

21 Citations (Scopus)

Abstract

A novel approach to the SSR channel profile formation for MOSFETs is suggested, with dopant implantation in the late stages of the processing, with the gate, source/drain already in (`TGi'). Only a single damage/activation anneal and the back-end thermal budget are experienced by the implanted dopants, which results in steep profiles even when light boron ions are used. High-performance NMOS devices with excellent SCE control designed for low-voltage digital, analog and RF operation were realized using this technique. For PMOS the use of TGi is restricted by significant diffusion of source/drain extensions due to the TGi damage induced TED.

Original language	English
Title of host publication	1998 IEEE International Electron Devices Meeting
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	635-638
Number of pages	4
ISBN (Print)	0-7803-4774-9
DOIs	https://doi.org/10.1109/IEDM.1998.746438
Publication status	Published - 1 Dec 1998
Externally published	Yes
Event	1998 IEEE International Electron Devices Meeting, IEDM 1998 - San Francisco, United States Duration: 6 Dec 1998 → 9 Dec 1998

Conference

Conference	1998 IEEE International Electron Devices Meeting, IEDM 1998
Abbreviated title	IEDM 1998
Country/Territory	United States
City	San Francisco
Period	6/12/98 → 9/12/98

Access to Document

10.1109/IEDM.1998.746438

Cite this

@inproceedings{585ab017ea3a41e6bfa61ded78490152,

title = "Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation",

abstract = "A novel approach to the SSR channel profile formation for MOSFETs is suggested, with dopant implantation in the late stages of the processing, with the gate, source/drain already in (`TGi'). Only a single damage/activation anneal and the back-end thermal budget are experienced by the implanted dopants, which results in steep profiles even when light boron ions are used. High-performance NMOS devices with excellent SCE control designed for low-voltage digital, analog and RF operation were realized using this technique. For PMOS the use of TGi is restricted by significant diffusion of source/drain extensions due to the TGi damage induced TED.",

author = "Ponomarev, \{Y. V.\} and Stolk, \{P. A.\} and \{van Brandenburg\}, \{A. C.M.C.\} and R. Roes and Montree, \{A. H.\} and J. Schmitz and Woerlee, \{P. H.\}",

year = "1998",

month = dec,

day = "1",

doi = "10.1109/IEDM.1998.746438",

language = "English",

isbn = "0-7803-4774-9",

pages = "635--638",

booktitle = "1998 IEEE International Electron Devices Meeting",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "1998 IEEE International Electron Devices Meeting, IEDM 1998, IEDM 1998 ; Conference date: 06-12-1998 Through 09-12-1998",

}

Ponomarev, YV, Stolk, PA, van Brandenburg, ACMC, Roes, R, Montree, AH, Schmitz, J & Woerlee, PH 1998, Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation. in 1998 IEEE International Electron Devices Meeting. Institute of Electrical and Electronics Engineers, Piscataway, pp. 635-638, 1998 IEEE International Electron Devices Meeting, IEDM 1998, San Francisco, California, United States, 6/12/98. https://doi.org/10.1109/IEDM.1998.746438

Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation. / Ponomarev, Y. V.; Stolk, P. A.; van Brandenburg, A. C.M.C. et al.
1998 IEEE International Electron Devices Meeting. Piscataway: Institute of Electrical and Electronics Engineers, 1998. p. 635-638.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation

AU - Ponomarev, Y. V.

AU - Stolk, P. A.

AU - van Brandenburg, A. C.M.C.

AU - Roes, R.

AU - Montree, A. H.

AU - Schmitz, J.

AU - Woerlee, P. H.

PY - 1998/12/1

Y1 - 1998/12/1

N2 - A novel approach to the SSR channel profile formation for MOSFETs is suggested, with dopant implantation in the late stages of the processing, with the gate, source/drain already in (`TGi'). Only a single damage/activation anneal and the back-end thermal budget are experienced by the implanted dopants, which results in steep profiles even when light boron ions are used. High-performance NMOS devices with excellent SCE control designed for low-voltage digital, analog and RF operation were realized using this technique. For PMOS the use of TGi is restricted by significant diffusion of source/drain extensions due to the TGi damage induced TED.

AB - A novel approach to the SSR channel profile formation for MOSFETs is suggested, with dopant implantation in the late stages of the processing, with the gate, source/drain already in (`TGi'). Only a single damage/activation anneal and the back-end thermal budget are experienced by the implanted dopants, which results in steep profiles even when light boron ions are used. High-performance NMOS devices with excellent SCE control designed for low-voltage digital, analog and RF operation were realized using this technique. For PMOS the use of TGi is restricted by significant diffusion of source/drain extensions due to the TGi damage induced TED.

UR - https://www.scopus.com/pages/publications/0032266441

U2 - 10.1109/IEDM.1998.746438

DO - 10.1109/IEDM.1998.746438

M3 - Conference contribution

AN - SCOPUS:0032266441

SN - 0-7803-4774-9

SP - 635

EP - 638

BT - 1998 IEEE International Electron Devices Meeting

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 1998 IEEE International Electron Devices Meeting, IEDM 1998

Y2 - 6 December 1998 through 9 December 1998

ER -

Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation

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