Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation

Y. V. Ponomarev, P. A. Stolk, A. C.M.C. van Brandenburg, R. Roes, A. H. Montree, J. Schmitz, P. H. Woerlee

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

21 Citations (Scopus)

Abstract

A novel approach to the SSR channel profile formation for MOSFETs is suggested, with dopant implantation in the late stages of the processing, with the gate, source/drain already in (`TGi'). Only a single damage/activation anneal and the back-end thermal budget are experienced by the implanted dopants, which results in steep profiles even when light boron ions are used. High-performance NMOS devices with excellent SCE control designed for low-voltage digital, analog and RF operation were realized using this technique. For PMOS the use of TGi is restricted by significant diffusion of source/drain extensions due to the TGi damage induced TED.

Original languageEnglish
Title of host publication1998 IEEE International Electron Devices Meeting
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages635-638
Number of pages4
ISBN (Print)0-7803-4774-9
DOIs
Publication statusPublished - 1 Dec 1998
Externally publishedYes
Event1998 IEEE International Electron Devices Meeting, IEDM 1998 - San Francisco, United States
Duration: 6 Dec 19989 Dec 1998

Conference

Conference1998 IEEE International Electron Devices Meeting, IEDM 1998
Abbreviated titleIEDM 1998
Country/TerritoryUnited States
CitySan Francisco
Period6/12/989/12/98

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