Challenges in testing TSV-based 3D stacked ICs: test flows, test contents, and test access

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Abstract

Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) have many attractive benefits and hence are quickly gaining ground. Testing such products for manufacturing defects is still fraught with many challenges. This paper provides an overview of those challenges and their emerging solutions, categorized in the areas of (1) test flows, (2) test contents, and (3) test access.
Original languageEnglish
Title of host publication2010 IEEE Asia Pacific Conference on Circuits and Systems
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages544-547
Number of pages4
ISBN (Electronic)978-1-4244-7456-1
ISBN (Print)978-1-4244-7454-7
DOIs
Publication statusPublished - Dec 2010
Externally publishedYes
Event2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010) - Kuala Lumpur, Malaysia
Duration: 6 Dec 20109 Dec 2010

Conference

Conference2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010)
Abbreviated titleAPCCAS 2010
CountryMalaysia
CityKuala Lumpur
Period6/12/109/12/10

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