Abstract
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) have many attractive benefits and hence are quickly gaining ground. Testing such products for manufacturing defects is still fraught with many challenges. This paper provides an overview of those challenges and their emerging solutions, categorized in the areas of (1) test flows, (2) test contents, and (3) test access.
Original language | English |
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Title of host publication | 2010 IEEE Asia Pacific Conference on Circuits and Systems |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 544-547 |
Number of pages | 4 |
ISBN (Electronic) | 978-1-4244-7456-1 |
ISBN (Print) | 978-1-4244-7454-7 |
DOIs | |
Publication status | Published - Dec 2010 |
Externally published | Yes |
Event | 2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010) - Kuala Lumpur, Malaysia Duration: 6 Dec 2010 → 9 Dec 2010 |
Conference
Conference | 2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010) |
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Abbreviated title | APCCAS 2010 |
Country/Territory | Malaysia |
City | Kuala Lumpur |
Period | 6/12/10 → 9/12/10 |