Challenges in testing TSV-based 3D stacked ICs: test flows, test contents, and test access

E.J. Marinissen

doi:10.1109/APCCAS.2010.5775087

Challenges in testing TSV-based 3D stacked ICs: test flows, test contents, and test access

E.J. Marinissen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

39 Citations (Scopus)

506 Downloads (Pure)

Abstract

Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) have many attractive benefits and hence are quickly gaining ground. Testing such products for manufacturing defects is still fraught with many challenges. This paper provides an overview of those challenges and their emerging solutions, categorized in the areas of (1) test flows, (2) test contents, and (3) test access.

Original language	English
Title of host publication	2010 IEEE Asia Pacific Conference on Circuits and Systems
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	544-547
Number of pages	4
ISBN (Electronic)	978-1-4244-7456-1
ISBN (Print)	978-1-4244-7454-7
DOIs	https://doi.org/10.1109/APCCAS.2010.5775087
Publication status	Published - Dec 2010
Externally published	Yes
Event	2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010) - Kuala Lumpur, Malaysia Duration: 6 Dec 2010 → 9 Dec 2010

Conference

Conference	2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010)
Abbreviated title	APCCAS 2010
Country/Territory	Malaysia
City	Kuala Lumpur
Period	6/12/10 → 9/12/10

Access to Document

10.1109/APCCAS.2010.5775087

apccas10Final author version , 319 KB

Cite this

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title = "Challenges in testing TSV-based 3D stacked ICs: test flows, test contents, and test access",

abstract = "Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) have many attractive benefits and hence are quickly gaining ground. Testing such products for manufacturing defects is still fraught with many challenges. This paper provides an overview of those challenges and their emerging solutions, categorized in the areas of (1) test flows, (2) test contents, and (3) test access.",

author = "E.J. Marinissen",

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doi = "10.1109/APCCAS.2010.5775087",

language = "English",

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booktitle = "2010 IEEE Asia Pacific Conference on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers",

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note = "2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010), APCCAS 2010 ; Conference date: 06-12-2010 Through 09-12-2010",

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Marinissen, EJ 2010, Challenges in testing TSV-based 3D stacked ICs: test flows, test contents, and test access. in 2010 IEEE Asia Pacific Conference on Circuits and Systems . Institute of Electrical and Electronics Engineers, Piscataway, pp. 544-547, 2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010), Kuala Lumpur, Malaysia, 6/12/10. https://doi.org/10.1109/APCCAS.2010.5775087

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AU - Marinissen, E.J.

PY - 2010/12

Y1 - 2010/12

N2 - Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) have many attractive benefits and hence are quickly gaining ground. Testing such products for manufacturing defects is still fraught with many challenges. This paper provides an overview of those challenges and their emerging solutions, categorized in the areas of (1) test flows, (2) test contents, and (3) test access.

AB - Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) have many attractive benefits and hence are quickly gaining ground. Testing such products for manufacturing defects is still fraught with many challenges. This paper provides an overview of those challenges and their emerging solutions, categorized in the areas of (1) test flows, (2) test contents, and (3) test access.

U2 - 10.1109/APCCAS.2010.5775087

DO - 10.1109/APCCAS.2010.5775087

M3 - Conference contribution

SN - 978-1-4244-7454-7

SP - 544

EP - 547

BT - 2010 IEEE Asia Pacific Conference on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010)

Y2 - 6 December 2010 through 9 December 2010

ER -

Challenges in testing TSV-based 3D stacked ICs: test flows, test contents, and test access

Abstract

Conference

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