Abstract
The linearity of Sigma Delta Modulators (SDMs) is typically evaluated by performing a Fourier Transform of the output bitstream. However, the presence of quantization noise in the output bitstream complicates this task: many samples and lengthy simulations are needed to lower this noise floor and evaluate the signal harmonics. We present here a method to estimate the quantization noise in the presence of non-linearity, remove it from the SDM bitstream, and reduce the number of samples needed to quantify the SDM linearity. By applying the proposed technique to a behavioral model of a 4th-order SDM, the accuracy of the linearity estimation is kept unchanged using 5000x less bitstream samples. This in turn can significantly reduce the SDM verification time.
| Original language | English |
|---|---|
| Pages (from-to) | 1862-1866 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 72 |
| Issue number | 12 |
| DOIs | |
| Publication status | Published - Dec 2025 |
Bibliographical note
Publisher Copyright:© 2004-2012 IEEE.
Keywords
- A/D conversion
- quantization errors
- Sigma-Delta modulation
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