Built-in current sensor for ΔIDDQ testing of deep submicron digital CMOS ICs

J.R. Vazquez, J. Pineda de Gyvez

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    3 Citations (Scopus)
    136 Downloads (Pure)


    This paper presents the implementation of a built-in current sensor that includes two recently reported new techniques for IDDQ testing to take into account the increased background current of defect-free circuits and its increased variance due to process variations. These techniques are the correlation between speed and IDDQ, and the ¿IDDQ testing technique. The monitor has been manufactured in a 0.18 µm CMOS technology and it is based on the principle of disconnecting the device under test from the power supply during the testing phase. The monitor has a resolution of 1 µA for a background current less than 100 µA or 1% of background currents over 100 µA to a total of 1 mA fullscale. The sensor operates at a maximum clock speed of 250 MHz. The monitor has been verified in a test chip consisting of one "DSP like" circuit of about 250,000 transistors. Experimental results prove the usefulness of our approach as a quick and effective means for detecting defects.
    Original languageEnglish
    Title of host publicationProceedings of the 22nd IEEE VLSI Test Symposium, 2004, 25-29 April 2004, Nappa Valley, California
    Place of PublicationNew York
    PublisherInstitute of Electrical and Electronics Engineers
    ISBN (Print)0-7695-2134-7
    Publication statusPublished - 2004


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