BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Abstract

In this paper we introduce and discuss the BuildMaster framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluation of selected designs. In each of the experiments we performed, we were able to reduce the number of required simulations with over 90% and save up to 50% on the required compilation time.
Original languageEnglish
Title of host publicationProceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages83-88
ISBN (Print)978-1-4799-4560-3
DOIs
Publication statusPublished - 2014
Eventconference; DDECS'14; 2014-04-23; 2014-04-25 -
Duration: 23 Apr 201425 Apr 2014

Conference

Conferenceconference; DDECS'14; 2014-04-23; 2014-04-25
Period23/04/1425/04/14
OtherDDECS'14

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Experiments

Cite this

Jordans, R., Diken, E., Jozwiak, L., & Corporaal, H. (2014). BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching. In Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland (pp. 83-88). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/DDECS.2014.6868768
Jordans, R. ; Diken, E. ; Jozwiak, L. ; Corporaal, H. / BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching. Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland. Piscataway : Institute of Electrical and Electronics Engineers, 2014. pp. 83-88
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Jordans, R, Diken, E, Jozwiak, L & Corporaal, H 2014, BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching. in Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland. Institute of Electrical and Electronics Engineers, Piscataway, pp. 83-88, conference; DDECS'14; 2014-04-23; 2014-04-25, 23/04/14. https://doi.org/10.1109/DDECS.2014.6868768

BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching. / Jordans, R.; Diken, E.; Jozwiak, L.; Corporaal, H.

Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland. Piscataway : Institute of Electrical and Electronics Engineers, 2014. p. 83-88.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Jordans R, Diken E, Jozwiak L, Corporaal H. BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching. In Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland. Piscataway: Institute of Electrical and Electronics Engineers. 2014. p. 83-88 https://doi.org/10.1109/DDECS.2014.6868768