Abstract
| Original language | English |
|---|---|
| Title of host publication | Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 83-88 |
| ISBN (Print) | 978-1-4799-4560-3 |
| DOIs | |
| Publication status | Published - 2014 |
| Event | conference; DDECS'14; 2014-04-23; 2014-04-25 - Duration: 23 Apr 2014 → 25 Apr 2014 |
Conference
| Conference | conference; DDECS'14; 2014-04-23; 2014-04-25 |
|---|---|
| Period | 23/04/14 → 25/04/14 |
| Other | DDECS'14 |
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BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching. / Jordans, R.; Diken, E.; Jozwiak, L.; Corporaal, H.
Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland. Piscataway : Institute of Electrical and Electronics Engineers, 2014. p. 83-88.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching
AU - Jordans, R.
AU - Diken, E.
AU - Jozwiak, L.
AU - Corporaal, H.
PY - 2014
Y1 - 2014
N2 - In this paper we introduce and discuss the BuildMaster framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluation of selected designs. In each of the experiments we performed, we were able to reduce the number of required simulations with over 90% and save up to 50% on the required compilation time.
AB - In this paper we introduce and discuss the BuildMaster framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluation of selected designs. In each of the experiments we performed, we were able to reduce the number of required simulations with over 90% and save up to 50% on the required compilation time.
U2 - 10.1109/DDECS.2014.6868768
DO - 10.1109/DDECS.2014.6868768
M3 - Conference contribution
SN - 978-1-4799-4560-3
SP - 83
EP - 88
BT - Proceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland
PB - Institute of Electrical and Electronics Engineers
CY - Piscataway
ER -