BuildMaster : efficient ASIP architecture exploration through compilation and simulation result caching

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Abstract

In this paper we introduce and discuss the BuildMaster framework. This framework supports the design space exploration of application specific VLIW processors and offers automated caching of intermediate compilation and simulation results. Both the compilation and the simulation cache can greatly help to shorten the exploration time and make it possible to use more realistic data for the evaluation of selected designs. In each of the experiments we performed, we were able to reduce the number of required simulations with over 90% and save up to 50% on the required compilation time.
Original languageEnglish
Title of host publicationProceedings on the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'14), 23-25 April 2014, Warsaw, Poland
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages83-88
ISBN (Print)978-1-4799-4560-3
DOIs
Publication statusPublished - 2014
Eventconference; DDECS'14; 2014-04-23; 2014-04-25 -
Duration: 23 Apr 201425 Apr 2014

Conference

Conferenceconference; DDECS'14; 2014-04-23; 2014-04-25
Period23/04/1425/04/14
OtherDDECS'14

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