Bridging the gap between IC design and its application

Mart Coenen

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review


IC ESD protection measures need to combine the handling constraints effectively without causing any functional drawback to its foreseen application. With today’s nanometer processes, the vulnerability of the circuits to be protected increases, though on the opposite side the RF immunity requirements, are enhanced for the so called ‘global’ pins at the application level. Questions need to be answered on what can and has to be done at the application, in the package and on-silicon to close this gap efficiently while being able to demonstrate compliance to the ESD standards applicable at the various verification levels concerned.
Original languageEnglish
Title of host publicationProceedings of the International Electrostatic Discharge Workshop (ESDA/IEW 2012), May 14-17, 2012 Oud-Turnhout, Belgium
Place of PublicationRome
PublisherESD Association
ISBN (Print)1-58537-218-8
Publication statusPublished - 2012
Eventconference; ESDA/IEW 2012 - Belgie, Oud-Turnhout - May 2012 -
Duration: 1 Jan 2012 → …


Conferenceconference; ESDA/IEW 2012 - Belgie, Oud-Turnhout - May 2012
Period1/01/12 → …
OtherESDA/IEW 2012 - Belgie, Oud-Turnhout - May 2012


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