Bridging the gap between IC design and its application

IC ESD protection measures need to combine the handling constraints effectively without causing any functional drawback to its foreseen application. With today’s nanometer processes, the vulnerability of the circuits to be protected increases, though on the opposite side the RF immunity requirements, are enhanced for the so called ‘global’ pins at the application level. Questions need to be answered on what can and has to be done at the application, in the package and on-silicon to close this gap efficiently while being able to demonstrate compliance to the ESD standards applicable at the various verification levels concerned.