BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport Triggered NN SoC

Maarten Molendijk; Floran de Putter; M.D. Gomony; Pekka O. Jaaskelainen; Henk Corporaal

doi:10.1109/ICCD58817.2023.00022

BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport Triggered NN SoC

Maarten Molendijk, Floran de Putter, M.D. Gomony, Pekka O. Jaaskelainen, Henk Corporaal

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

11 Downloads (Pure)

Abstract

Accelerators designed for deep neural network (DNN) inference with extremely low operand widths, down to 1-bit, have become popular due to their ability to significantly reduce energy consumption during inference. This paper introduces a compiler-programmable flexible System-on-Chip (SoC) with mixed-precision support. This SoC is based on a Transport-Triggered Architecture (TTA) that facilitates efficient implementation of DNN workloads. By shifting the complexity of data movement from the hardware scheduler to the exposed-datapath compiler, DNN workloads can be implemented in an energy efficient yet flexible way. The architecture is fully supported by a compiler and can be programmed using C/C++/OpenCL. The SoC is implemented using 22nm FDX technology and achieves a peak energy efficiency of 28.6/14.9/2.47 TOPS/W for binary, ternary, and 8-bit precision, respectively, while delivering a throughput of 614/307/77 GOPS. Compared to state-of-the-art (SotA), this work achieves up to 3.3x better energy efficiency compared to other programmable solutions.

Original language	English
Title of host publication	2023 IEEE International Conference on Computer Design (ICCD)
Publisher	Institute of Electrical and Electronics Engineers
Pages	78-85
Number of pages	8
ISBN (Electronic)	979-8-3503-4291-8
DOIs	https://doi.org/10.1109/ICCD58817.2023.00022
Publication status	Published - 22 Dec 2023
Event	41st IEEE International Conference on Computer Design, ICCD 2023 - Washington, United States Duration: 6 Nov 2023 → 8 Nov 2023

Conference

Conference	41st IEEE International Conference on Computer Design, ICCD 2023
Abbreviated title	ICCD 2023
Country/Territory	United States
City	Washington
Period	6/11/23 → 8/11/23

Keywords

Binary neural network
Ternary neural network
deep learning
edge computing
low power inference
mixed precision accelerator
neural network accelerator

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ICCD58817.2023.00022

Cite this

@inproceedings{5fe5e092cb104af39a5300c257005043,

title = "BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport Triggered NN SoC",

abstract = "Accelerators designed for deep neural network (DNN) inference with extremely low operand widths, down to 1-bit, have become popular due to their ability to significantly reduce energy consumption during inference. This paper introduces a compiler-programmable flexible System-on-Chip (SoC) with mixed-precision support. This SoC is based on a Transport-Triggered Architecture (TTA) that facilitates efficient implementation of DNN workloads. By shifting the complexity of data movement from the hardware scheduler to the exposed-datapath compiler, DNN workloads can be implemented in an energy efficient yet flexible way. The architecture is fully supported by a compiler and can be programmed using C/C++/OpenCL. The SoC is implemented using 22nm FDX technology and achieves a peak energy efficiency of 28.6/14.9/2.47 TOPS/W for binary, ternary, and 8-bit precision, respectively, while delivering a throughput of 614/307/77 GOPS. Compared to state-of-the-art (SotA), this work achieves up to 3.3x better energy efficiency compared to other programmable solutions.",

keywords = "Binary neural network, Ternary neural network, deep learning, edge computing, low power inference, mixed precision accelerator, neural network accelerator",

author = "Maarten Molendijk and {de Putter}, Floran and M.D. Gomony and Jaaskelainen, {Pekka O.} and Henk Corporaal",

year = "2023",

month = dec,

day = "22",

doi = "10.1109/ICCD58817.2023.00022",

language = "English",

pages = "78--85",

booktitle = "2023 IEEE International Conference on Computer Design (ICCD)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "41st IEEE International Conference on Computer Design, ICCD 2023, ICCD 2023 ; Conference date: 06-11-2023 Through 08-11-2023",

}

Molendijk, M , de Putter, F , Gomony, MD, Jaaskelainen, PO & Corporaal, H 2023, BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport Triggered NN SoC. in 2023 IEEE International Conference on Computer Design (ICCD)., 10361002, Institute of Electrical and Electronics Engineers, pp. 78-85, 41st IEEE International Conference on Computer Design, ICCD 2023, Washington, United States, 6/11/23. https://doi.org/10.1109/ICCD58817.2023.00022

BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport Triggered NN SoC. / Molendijk, Maarten ; de Putter, Floran ; Gomony, M.D. et al.
2023 IEEE International Conference on Computer Design (ICCD). Institute of Electrical and Electronics Engineers, 2023. p. 78-85 10361002.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - BrainTTA

T2 - 41st IEEE International Conference on Computer Design, ICCD 2023

AU - Molendijk, Maarten

AU - de Putter, Floran

AU - Gomony, M.D.

AU - Jaaskelainen, Pekka O.

AU - Corporaal, Henk

PY - 2023/12/22

Y1 - 2023/12/22

N2 - Accelerators designed for deep neural network (DNN) inference with extremely low operand widths, down to 1-bit, have become popular due to their ability to significantly reduce energy consumption during inference. This paper introduces a compiler-programmable flexible System-on-Chip (SoC) with mixed-precision support. This SoC is based on a Transport-Triggered Architecture (TTA) that facilitates efficient implementation of DNN workloads. By shifting the complexity of data movement from the hardware scheduler to the exposed-datapath compiler, DNN workloads can be implemented in an energy efficient yet flexible way. The architecture is fully supported by a compiler and can be programmed using C/C++/OpenCL. The SoC is implemented using 22nm FDX technology and achieves a peak energy efficiency of 28.6/14.9/2.47 TOPS/W for binary, ternary, and 8-bit precision, respectively, while delivering a throughput of 614/307/77 GOPS. Compared to state-of-the-art (SotA), this work achieves up to 3.3x better energy efficiency compared to other programmable solutions.

AB - Accelerators designed for deep neural network (DNN) inference with extremely low operand widths, down to 1-bit, have become popular due to their ability to significantly reduce energy consumption during inference. This paper introduces a compiler-programmable flexible System-on-Chip (SoC) with mixed-precision support. This SoC is based on a Transport-Triggered Architecture (TTA) that facilitates efficient implementation of DNN workloads. By shifting the complexity of data movement from the hardware scheduler to the exposed-datapath compiler, DNN workloads can be implemented in an energy efficient yet flexible way. The architecture is fully supported by a compiler and can be programmed using C/C++/OpenCL. The SoC is implemented using 22nm FDX technology and achieves a peak energy efficiency of 28.6/14.9/2.47 TOPS/W for binary, ternary, and 8-bit precision, respectively, while delivering a throughput of 614/307/77 GOPS. Compared to state-of-the-art (SotA), this work achieves up to 3.3x better energy efficiency compared to other programmable solutions.

KW - Binary neural network

KW - Ternary neural network

KW - deep learning

KW - edge computing

KW - low power inference

KW - mixed precision accelerator

KW - neural network accelerator

UR - http://www.scopus.com/inward/record.url?scp=85182321229&partnerID=8YFLogxK

U2 - 10.1109/ICCD58817.2023.00022

DO - 10.1109/ICCD58817.2023.00022

M3 - Conference contribution

SP - 78

EP - 85

BT - 2023 IEEE International Conference on Computer Design (ICCD)

PB - Institute of Electrical and Electronics Engineers

Y2 - 6 November 2023 through 8 November 2023

ER -

BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport Triggered NN SoC

Abstract

Conference

Keywords

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this