Worst-case design uses extreme process corner conditions which rarely occur. This costs additional power due to area over-dimensioning during synthesis. We present a new design strategy for digital CMOS IP that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. Dynamic power is reduced depending upon the ratio of flip-flops to logic-gates, and data activity. On a set of benchmark circuits in 65 nm LP-CMOS, we observed performance-per-area improvements up to 81%, area and leakage reductions up to 38%, and total power savings of up to 26% without performance penalties.
|Title of host publication||Proceedings of the 2010 11th International Symposium on Quality Electronic Design (ISQED), 22-24 March 2010, San Jose, California|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2010|