Blocks: Redesigning coarse grained reconfigurable architectures for energy efficiency

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Demand for coarse grain reconfigurable architectures has significantly increased as architectures need to be both energy efficient and flexible. However, most CGRAs are optimized for performance instead of energy efficiency. In this work Blocks is presented. Blocks uses two separate circuit-switched networks, one for control and one for the data-path. The unique structure of these networks enables run-time construction of energy-efficient application-specific VLIW-SIMD processors. Energy efficiency is demonstrated by comparing Blocks to a traditional CGRA on 40nm layout. Results show an energy overhead reduction between 46% and 76% and total energy reduction between 9% and 29%, depending on the benchmark. Demonstrating that the cost of flexibility can be lower than might be expected.

Original languageEnglish
Title of host publicationProceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019
EditorsIoannis Sourdis, Christos-Savvas Bouganis, Carlos Alvarez, Leonel Antonio Toledo Diaz, Pedro Valero, Xavier Martorell
PublisherInstitute of Electrical and Electronics Engineers
Number of pages7
ISBN (Electronic)9781728148847
Publication statusPublished - Sep 2019
Event29th International Conferenceon Field-Programmable Logic and Applications, FPL 2019 - Barcelona, Spain
Duration: 9 Sep 201913 Sep 2019


Conference29th International Conferenceon Field-Programmable Logic and Applications, FPL 2019


  • CGRA
  • Energy Efficiency
  • Reconfigurable Architecture

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