Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture

M. Wijtvliet (Corresponding author), A. Kumar, H. Corporaal

Research output: Contribution to journalArticleAcademicpeer-review

4 Citations (Scopus)
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Demand for coarse grain reconfigurable architectures (CGRAs) has significantly increased in recent years as architectures need to be both energy efficient and flexible. However, most CGRAs are optimized for performance instead of energy efficiency. In this work, a novel paradigm for reconfigurable architectures, Blocks, is presented. Blocks uses two separate circuit-switched networks, one for control and one for the data path. This enables the runtime construction of energy-efficient application-specific VLIW-SIMD processors on a reconfigurable fabric. Its energy efficiency is demonstrated by comparing Blocks to four reference architectures, a VLIW, an SIMD, a commercial low-power microprocessor, and a traditional CGRA. All comparisons are based on commercial low-power 40-nm CMOS layout, including memories. Results show that Blocks can achieve a mean total energy reduction of 2.05 × , 1.84 × , 8.01 × , and 1.22 × over a VLIW, an SIMD, an energy-efficient microprocessor and a traditional CGRA, respectively. At the same time, Blocks delivers equal or higher performance per area due to its ability to adapt to applications by reconfiguration.

Original languageEnglish
Article number9576514
Pages (from-to)2915-2928
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number9
Publication statusPublished - 1 Sept 2022


  • Coarse grain reconfigurable architecture (CGRA)
  • energy efficiency
  • reconfigurable architecture


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