Bayesian optimization for Tuning Lithography Processes

Sila Guler, Maarten Schoukens, Taciano Dreckmann Perez, Jerzy Husakowski

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Abstract

Lithography processes have advanced steps that need to be controlled accurately in order to achieve high production quality. The common approach is to have a setup phase in which the optimal parameters for each step of the process are explored manually by an operator. This paper introduces a process parameter selection system that can automate this exploration phase. Since a semiconductor manufacturing process is too complex to model mathematically as a whole, a model-based optimization technique is not preferred. Instead, a Gaussian process (GP) based Bayesian optimization (BO) method is applied to optimize the process parameters automatically. This method is designed according to the lithography process domain. To validate the performance of the GP based BO method, optimization experiments are run for eight different manufacturing processes. The results demonstrate that GP based BO obtains better process parameters that reduce the overlay error, an important quality metric, by 6.01% or 0.4 nm compared to the one achieved with the manual parameter selection process. Furthermore, the automated process parameter optimization requires much less expert user knowledge and can be completed in a shorter time. Considering the fact that the semiconductor manufacturers compete with each other with nanometric differences in features of their integrated circuit (IC) designs, this improvement could give a significant advantage in practical applications.

Original languageEnglish
Pages (from-to)827-832
Number of pages6
JournalIFAC-PapersOnLine
Volume54
Issue number7
DOIs
Publication statusPublished - 1 Jul 2021
Event19th IFAC Symposium on System Identification, SYSID 2021 - Virtual, Padova, Italy
Duration: 13 Jul 202116 Jul 2021
Conference number: 19
https://www.sysid2021.org/

Keywords

  • Applications in Semiconductor Manufacturing
  • Bayesian optimization
  • Process Tuning

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