Bandwidth analysis for reusing functional interconnect as test access mechanism

A. van den Berg, P. Ren, E.J. Marinissen, G.N. Gaydadjiev, K.G.W. Goossens

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

8 Citations (Scopus)
136 Downloads (Pure)


Test data travels through a System-on-Chip (SOC) from the chip pins to the module-under-test and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented with dedicated wires. However, also existing functional interconnect, such as a bus or Network-on-Chip (NOC), can be reused as TAM. This will reduce the overall design effort and the silicon area. For a given module, its test set, and maximal bandwidth that the functional interconnect can offer between ATE and module-under-test, our approach designs a test wrapper for the module-under-test such that the test length is minimized. Unfortunately, it is unavoidable that with the test data also unused (idle) bits are transported. This paper presents a TAM bandwidth utilization analysis and techniques for idle bits reduction, to minimize the test length. We classify the idle bits into four types which explain the reason for bandwidth under-utilization and pinpoint design improvement opportunities. Experimental results show an average bandwidth utilization of 80%, while the remaining 20% is consumed by the idle bits. © 2008 IEEE.
Original languageEnglish
Title of host publication2008 13th European Test Symposium
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages6
ISBN (Print)978-0-7695-3150-2
Publication statusPublished - 2008
Event13th IEEE European Test Symposium (ETS 2008) - Verbania, Italy
Duration: 25 May 200829 May 2008


Conference13th IEEE European Test Symposium (ETS 2008)


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