Average leakage current estimation of CMOS logic circuits

J. Pineda de Gyvez, E. Wetering, van der

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    7 Citations (Scopus)
    83 Downloads (Pure)

    Abstract

    In a product engineering environment there is a need to know quickly the average standby current of an IC for various combinations of power supply and temperature. We present two techniques to do this estimation without resorting to involved simulations. We use a bottom-up methodology that propagates the effect of process variations to higher levels of abstraction. In one approach, the leakage current of any given circuit is computed by adding up individual cell currents indexed from a statistically characterized library of standard cells. The second method is based on empirical formulae derived from results of the standard cell library characterization. In this approach the total leakage current is estimated without the need for any simulations and using only the circuit's equivalent cell-count. We present here the statistical foundation of our approach as well as experimental results on actual ICs
    Original languageEnglish
    Title of host publicationProceedings on 19th IEEE VLSI Test Symposium, VTS 2001, 29 April - 3 May 2001, Marina del Rey, California
    Place of PublicationNew York
    PublisherInstitute of Electrical and Electronics Engineers
    Pages375-379
    ISBN (Print)0-7695-1122-8
    DOIs
    Publication statusPublished - 2001

    Fingerprint Dive into the research topics of 'Average leakage current estimation of CMOS logic circuits'. Together they form a unique fingerprint.

  • Cite this

    Pineda de Gyvez, J., & Wetering, van der, E. (2001). Average leakage current estimation of CMOS logic circuits. In Proceedings on 19th IEEE VLSI Test Symposium, VTS 2001, 29 April - 3 May 2001, Marina del Rey, California (pp. 375-379). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VTS.2001.923465