Custom instruction identification is an essential part in designing efficient application-specific instruction set processors (ASIPs). Basically, the identification process consists of profiling the application of interest to find the frequently executed sub-sets of basic operations that can be implemented as a single custom instruction in the ASIP datapath. This accelerates the execution of the given application, or even of a set of applications of the same domain. However, a naive ad hoc instruction set customization process may not result in a significantly improved performance with low circuit area and energy consumption footprints. In this work, we propose and discuss a novel efficient instruction set customization method implemented as an automatic tool that is able to identify promising custom instruction candidates for a set of relevant benchmark applications. The proposed method formulates the common subgraph enumeration problem as a maximum clique-enumeration problem, with a twofold novel contribution: accounting for the connectivity aspect; and the graph associativity detection. The performance results are provided for the usage of the proposed tool for a configurable commercially available VLIW-ASIP for configurations of up to three augmented issue-slots, achieving a speedup of up to 54 % for the ray-tracing application. Circuit area and energy consumption results based on the TSMC 65 nm technology are also presented. The obtained results are compared to those reported in related works.
- Custom instruction
- Maximum clique enumeration