Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application

J. Liang; J. Lee; S. Berrada; V. Georgiev; A. Asenov; N. Azemard-Crestani; A. Todri-Sanial

doi:10.1109/NMDC.2017.8350506

Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application

J. Liang
, J. Lee
, S. Berrada
, V. Georgiev
, A. Asenov
, N. Azemard-Crestani
, A. Todri-Sanial

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

Carbon nanotubes (CNTs) due to their high electrical/thermal conductivity, high ampacity, high tolerance to electro-migration [1] and small dimensions make them an ideal candidate for future on-chip interconnects [2]. Fabricating the CNTs, random chirality and some defects are introduced which can degrade the CNT electrical properties [3]. Additionally, the contact resistance between metal and CNT presents additional parasitics that impose restraints on the electron transport. Electrical models of CNT for interconnect application were developed several years ago [4-5]. In this paper, we explored on doped and defective single-wall CNTs (SWCNT (24,0)) including contact resistance as important physical parameters to assess the performance of fabricated SWCNTs realistically for back-end-of-line (BEOL) on-chip interconnects on VLSI circuit application.

Original language	English
Title of host publication	2017 IEEE 12th Nanotechnology Materials and Devices Conference, NMDC 2017
Publisher	Institute of Electrical and Electronics Engineers
Pages	66-67
Number of pages	2
ISBN (Electronic)	9781538627723
DOIs	https://doi.org/10.1109/NMDC.2017.8350506
Publication status	Published - 26 Apr 2018
Externally published	Yes
Event	12th IEEE Nanotechnology Materials and Devices Conference, NMDC 2017 - Singapore, Singapore Duration: 2 Oct 2017 → 4 Oct 2017

Conference

Conference	12th IEEE Nanotechnology Materials and Devices Conference, NMDC 2017
Country/Territory	Singapore
City	Singapore
Period	2/10/17 → 4/10/17

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10.1109/NMDC.2017.8350506

Cite this

Liang, J., Lee, J., Berrada, S., Georgiev, V., Asenov, A., Azemard-Crestani, N., & Todri-Sanial, A. (2018). Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application. In 2017 IEEE 12th Nanotechnology Materials and Devices Conference, NMDC 2017 (pp. 66-67). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/NMDC.2017.8350506

@inproceedings{211955cb22cf4fb59e67d4c8cec0c020,

title = "Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application",

abstract = "Carbon nanotubes (CNTs) due to their high electrical/thermal conductivity, high ampacity, high tolerance to electro-migration [1] and small dimensions make them an ideal candidate for future on-chip interconnects [2]. Fabricating the CNTs, random chirality and some defects are introduced which can degrade the CNT electrical properties [3]. Additionally, the contact resistance between metal and CNT presents additional parasitics that impose restraints on the electron transport. Electrical models of CNT for interconnect application were developed several years ago [4-5]. In this paper, we explored on doped and defective single-wall CNTs (SWCNT (24,0)) including contact resistance as important physical parameters to assess the performance of fabricated SWCNTs realistically for back-end-of-line (BEOL) on-chip interconnects on VLSI circuit application.",

author = "J. Liang and J. Lee and S. Berrada and V. Georgiev and A. Asenov and N. Azemard-Crestani and A. Todri-Sanial",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 12th IEEE Nanotechnology Materials and Devices Conference, NMDC 2017 ; Conference date: 02-10-2017 Through 04-10-2017",

year = "2018",

month = apr,

day = "26",

doi = "10.1109/NMDC.2017.8350506",

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booktitle = "2017 IEEE 12th Nanotechnology Materials and Devices Conference, NMDC 2017",

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Liang, J, Lee, J, Berrada, S, Georgiev, V, Asenov, A, Azemard-Crestani, N & Todri-Sanial, A 2018, Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application. in 2017 IEEE 12th Nanotechnology Materials and Devices Conference, NMDC 2017. Institute of Electrical and Electronics Engineers, pp. 66-67, 12th IEEE Nanotechnology Materials and Devices Conference, NMDC 2017, Singapore, Singapore, 2/10/17. https://doi.org/10.1109/NMDC.2017.8350506

Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application. / Liang, J.; Lee, J.; Berrada, S. et al.
2017 IEEE 12th Nanotechnology Materials and Devices Conference, NMDC 2017. Institute of Electrical and Electronics Engineers, 2018. p. 66-67.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application

AU - Liang, J.

AU - Lee, J.

AU - Berrada, S.

AU - Georgiev, V.

AU - Asenov, A.

AU - Azemard-Crestani, N.

AU - Todri-Sanial, A.

PY - 2018/4/26

Y1 - 2018/4/26

N2 - Carbon nanotubes (CNTs) due to their high electrical/thermal conductivity, high ampacity, high tolerance to electro-migration [1] and small dimensions make them an ideal candidate for future on-chip interconnects [2]. Fabricating the CNTs, random chirality and some defects are introduced which can degrade the CNT electrical properties [3]. Additionally, the contact resistance between metal and CNT presents additional parasitics that impose restraints on the electron transport. Electrical models of CNT for interconnect application were developed several years ago [4-5]. In this paper, we explored on doped and defective single-wall CNTs (SWCNT (24,0)) including contact resistance as important physical parameters to assess the performance of fabricated SWCNTs realistically for back-end-of-line (BEOL) on-chip interconnects on VLSI circuit application.

AB - Carbon nanotubes (CNTs) due to their high electrical/thermal conductivity, high ampacity, high tolerance to electro-migration [1] and small dimensions make them an ideal candidate for future on-chip interconnects [2]. Fabricating the CNTs, random chirality and some defects are introduced which can degrade the CNT electrical properties [3]. Additionally, the contact resistance between metal and CNT presents additional parasitics that impose restraints on the electron transport. Electrical models of CNT for interconnect application were developed several years ago [4-5]. In this paper, we explored on doped and defective single-wall CNTs (SWCNT (24,0)) including contact resistance as important physical parameters to assess the performance of fabricated SWCNTs realistically for back-end-of-line (BEOL) on-chip interconnects on VLSI circuit application.

UR - https://www.scopus.com/pages/publications/85047991296

U2 - 10.1109/NMDC.2017.8350506

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M3 - Conference contribution

AN - SCOPUS:85047991296

SP - 66

EP - 67

BT - 2017 IEEE 12th Nanotechnology Materials and Devices Conference, NMDC 2017

PB - Institute of Electrical and Electronics Engineers

T2 - 12th IEEE Nanotechnology Materials and Devices Conference, NMDC 2017

Y2 - 2 October 2017 through 4 October 2017

ER -

Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application

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