At-speed testing of inter-die connections of 3D-SICs in the presence of shore logic

K. Shibin, V. Chickermane, B. Keller, C. Papameletis, E.J. Marinissen

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Abstract

Inter-die connections in 2.5D-and 3D-stacked ICs require at-speed testing as their dynamic performance is crucial to the performance of the stack as a whole. In order to test at mission-mode speed and benefit from the already existing clock distribution network, our at-speed test approach for inter-die connections targets the entire register-to-register path that includes the interconnect. This forces the launching and capturing wrapper cells to be shared with functional flip-flops. In some designs, this unavoidably leads to some 'shore logic': a, typically small, amount of combinational logic outside the die's wrapper boundary register. This paper describes how we have adapted a previously developed 3D-DfT architecture and corresponding EDA tool flows to support at-speed interconnect testing, also in the presence of such 'shore logic'. The adaptations affect the DfT insertion of wrapper cells, the boundary model extraction, and the interconnect test pattern generation.
Original languageEnglish
Title of host publicationIEEE 24th Asian Test Symposium, Mumbai, 22-25 November 2015
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages79-84
ISBN (Print)978-1-4673-9739-1
DOIs
Publication statusPublished - 2015
Externally publishedYes
Event24th IEEE Asian Test Symposium (ATS 2015) - IIT-Bombay, Mumbai, India
Duration: 22 Nov 201525 Nov 2015
Conference number: 24
https://www.ee.iitb.ac.in/ats15/

Conference

Conference24th IEEE Asian Test Symposium (ATS 2015)
Abbreviated titleATS 2015
CountryIndia
CityMumbai
Period22/11/1525/11/15
Internet address

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