The present invention is related to an analog to digital converter circuit. The circuit comprises at least one input node for applying an analog input voltage signal (Vin), means for sampling said analog input voltage signal, a first array of capacitors arranged for receiving the sampled analog input voltage signal, a digital delay line connected to the first array of capacitors and arranged for being enabled by a clock generator and for generating a staircase or slope function by means of the first capacitor array, taking into account the sampled analog input voltage signal, a comparator arranged for comparing a converted signal with a reference voltage (Vref), said converted signal being a version of said sampled analog input voltage converted according to said staircase or slope function, and for generating a stop signal based on the comparison result thereby latching the digital delay line and thereby acquiring the digital code.
|Patent number||EP2388923 (B1)|
|Publication status||Published - 4 Dec 2013|
Bibliographical noteAlso published as: