(AS)2 : accelerator synthesis using algorithmic skeletons for rapid design space exploration

S.D. Fernando, M. Wijtvliet, C. Nugteren, A. Kumar, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

5 Citations (Scopus)
135 Downloads (Pure)


Hardware accelerators in heterogeneous multiprocessor system-on-chips are becoming popular as a means of meeting performance and energy efficiency requirements of modern embedded systems. Current design methods for accelerator synthesis, such as High-Level Synthesis, are not fully automated. Therefore, time consuming manual iterations are required to explore efficient accelerator alternatives: the programmer is still required to think in terms of the underlying architecture. In this paper, we present (AS)2: a design flow for Accelerator Synthesis using Algorithmic Skeletons. Skeletonization separates the structure of a parallel computation from an algorithms' functionality, enabling efficient implementations without requiring the programmer to have hardware knowledge. We define three such skeletons (for three image processing kernels) enabling FPGA specific parallelization techniques and optimizations. As a case study, we present a design space exploration of these skeletons and show how multiple design points with area-performance trade-offs for the accelerators can be efficiently and rapidly synthesized. We show that (AS)2 is a promising direction for accelerator synthesis as it generates a pareto front of 8 design points in under half an hour for each of the three image processing kernels.
Original languageEnglish
Title of host publicationProceedings of the Conference on Design, Automation and Test in Europe (DATE 15) 9-13 March 2015, Grenoble, France
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Publication statusPublished - 2015
Event18th Design, Automation and Test in Europe Conference and Exhibition (DATE 2015) - Alpexpo Congress Centre, Grenoble, France
Duration: 9 Mar 201513 Mar 2015
Conference number: 18


Conference18th Design, Automation and Test in Europe Conference and Exhibition (DATE 2015)
Abbreviated titleDATE 2015
Internet address


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