Argo : a real-time network-on-chip architecture with an efficient GALS implementation

E. Kasapaki, M. Schoeberl, R.B. Sørensen, C. Müller, K.G.W. Goossens, J. Sparsø

Research output: Contribution to journalArticleAcademicpeer-review

65 Citations (Scopus)
26 Downloads (Pure)


In this paper, we present an area-efficient, globally asynchronous, locally synchronous network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC implements message-passing communication between processor cores. It uses statically scheduled time-division multiplexing (TDM) to control the communication over a structure of routers, links, and network interfaces (NIs) to offer real-time guarantees. The area-efficient design is a result of two contributions: 1) asynchronous routers combined with TDM scheduling and 2) a novel NI microarchitecture. Together they result in a design in which data are transferred in a pipelined fashion, from the local memory of the sending core to the local memory of the receiving core, without any dynamic arbitration, buffering, and clock synchronization. The routers use two-phase bundled-data handshake latches based on the Mousetrap latch controller and are extended with a clock gating mechanism to reduce the energy consumption. The NIs integrate the direct memory access functionality and the TDM schedule, and use dual-ported local memories to avoid buffering, flow-control, and synchronization. To verify the design, we have implemented a 4 times 4 bitorus NoC in 65-nm CMOS technology and we present results on area, speed, and energy consumption for the router, NI, NoC, and postlayout.

Original languageEnglish
Article number7064728
Pages (from-to)479-492
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number2
Publication statusPublished - 1 Feb 2016


  • Asynchronous design
  • multiprocessor interconnection networks
  • real-time systems
  • time-division multiplexing (TDM).


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