Architecture and optimal configuration of a real-time multi-channel memory controller

M.D. Gomony, K.B. Akesson, Kees Goossens

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

31 Citations (Scopus)


Optimal utilization of a multi-channel memory, such as Wide IO DRAM, as shared memory in multi-processor platforms depends on the mapping of memory clients to the memory channels, the granularity at which the memory requests are interleaved in each channel, and the bandwidth and memory capacity allocated to each memory client in each channel. Firm real-time applications in such platforms impose strict requirements on shared memory bandwidth and latency, which must be guaranteed at design-time to reduce verification effort. However, there is currently no real-time memory controller for multichannel memories, and there is no methodology to optimally configure multi-channel memories in real-time systems. This paper has four key contributions: (1) A real-time multi-channel memory controller architecture with a new programmable Multi-Channel Interleaver unit. (2) A novel method for logical-to-physical address translation that enables inter-leaving memory requests across multiple memory channels at different granularities. (3) An optimal algorithm based on an Integer Linear Program (ILP) formulation to map memory clients to memory channels considering their communication dependencies, and to configure the memory controller for minimum bandwidth utilization. (4) We experimentally evaluate the run-time of the algorithm and show that an optimal solution can be found within 15 minutes for realistically sized problems. We also demonstrate configuring a multi-channel Wide IO DRAM in a High-Definition (HD) video and graphics processing system to emphasize the effectiveness of our approach.
Original languageEnglish
Title of host publicationProceedings of Design, Automation & Test in Europe & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France
EditorsK. Preas
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages6
ISBN (Print)978-1-4673-5071-6
Publication statusPublished - 2013
Event16th Design, Automation and Test in Europe Conference and Exhibition (DATE 2013) - Grenoble, France
Duration: 18 Mar 201322 Mar 2013
Conference number: 16


Conference16th Design, Automation and Test in Europe Conference and Exhibition (DATE 2013)
Abbreviated titleDATE 2013
Internet address


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