Architecture and design flow for a debug event distribution interconnect.

A. Azevedo, H.G.H. Vermeulen, K.G.W. Goossens

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)


In this paper, we describe and analyze the architecture of the proposed Debug Event Distribution Interconnect (EDI). The EDI transmits debug events, which are 1-bit signals, between debug entities in different areas of the Network-on-Chip based Multi-Processor System-on-Chip. The EDI replicates the NoC topology with an EDI node instantiated for each underlying NoC data module. Contention in the EDI node is handled by replicating the EDI in layers. The EDI generation is automatic, and uses as input the cross-triggering patterns that are not required to follow the communication patterns in the NoC. The generation and routing tool is also presented in this paper. The EDI is evaluated with four different implementations varying complexity and handling of contention. The area of a single EDI Layer is around 0.9% of the area occupied by the tested NoCs, using the lower area implementation. These results show that the proposed implementation of the EDI incurs low cost on the overall system.
Original languageEnglish
Title of host publicationProceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD), 30 September - 2 October 2012, Montreal, Quebec
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Publication statusPublished - 2012
Event30th IEEE International Conference on Computer Design (ICCD 2012) - Montreal, Canada
Duration: 30 Sept 20123 Oct 2012
Conference number: 30


Conference30th IEEE International Conference on Computer Design (ICCD 2012)
Abbreviated titleICCD 2012
Internet address


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