Approaches and opportunities for area-selective atomic layer deposition

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Abstract

With conventional semiconductor fabrication based on top-down processing reaching its limits in terms of patterning resolution and alignment, there is increasing interest in the implementation of bottom-up fabrication steps. In this contribution, several approaches for bottom-up processing by area-selective atomic layer deposition (ALD) will be reviewed, and the application possibilities and the main challenges in the field will be discussed.

Original languageEnglish
Title of host publication2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages2
ISBN (Electronic)9781538648254
DOIs
Publication statusPublished - 3 Jul 2018
Event2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018 - Hsinchu, Taiwan
Duration: 16 Apr 201819 Apr 2018

Conference

Conference2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
CountryTaiwan
CityHsinchu
Period16/04/1819/04/18

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