Approaches and opportunities for area-selective atomic layer deposition

Adriaan J.M. Mackus

doi:10.1109/VLSI-TSA.2018.8403864

Approaches and opportunities for area-selective atomic layer deposition

Adriaan J.M. Mackus

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

1 Downloads (Pure)

Abstract

With conventional semiconductor fabrication based on top-down processing reaching its limits in terms of patterning resolution and alignment, there is increasing interest in the implementation of bottom-up fabrication steps. In this contribution, several approaches for bottom-up processing by area-selective atomic layer deposition (ALD) will be reviewed, and the application possibilities and the main challenges in the field will be discussed.

Original language	English
Title of host publication	2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	2
ISBN (Electronic)	9781538648254
DOIs	https://doi.org/10.1109/VLSI-TSA.2018.8403864
Publication status	Published - 3 Jul 2018
Event	2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018 - Hsinchu, Taiwan Duration: 16 Apr 2018 → 19 Apr 2018

Conference

Conference	2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
Country/Territory	Taiwan
City	Hsinchu
Period	16/04/18 → 19/04/18

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10.1109/VLSI-TSA.2018.8403864

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title = "Approaches and opportunities for area-selective atomic layer deposition",

abstract = "With conventional semiconductor fabrication based on top-down processing reaching its limits in terms of patterning resolution and alignment, there is increasing interest in the implementation of bottom-up fabrication steps. In this contribution, several approaches for bottom-up processing by area-selective atomic layer deposition (ALD) will be reviewed, and the application possibilities and the main challenges in the field will be discussed.",

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Mackus, AJM 2018, Approaches and opportunities for area-selective atomic layer deposition. in 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018., 8403864, Institute of Electrical and Electronics Engineers, Piscataway, 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018, Hsinchu, Taiwan, 16/04/18. https://doi.org/10.1109/VLSI-TSA.2018.8403864

Approaches and opportunities for area-selective atomic layer deposition. / Mackus, Adriaan J.M.
2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018. Piscataway: Institute of Electrical and Electronics Engineers, 2018. 8403864.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - With conventional semiconductor fabrication based on top-down processing reaching its limits in terms of patterning resolution and alignment, there is increasing interest in the implementation of bottom-up fabrication steps. In this contribution, several approaches for bottom-up processing by area-selective atomic layer deposition (ALD) will be reviewed, and the application possibilities and the main challenges in the field will be discussed.

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BT - 2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018

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ER -

Approaches and opportunities for area-selective atomic layer deposition

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