Abstract
A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with existing analysis algorithms, we
size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and
results comparable to exhaustive simulation.
Original language | English |
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Title of host publication | 2nd ACM/IEProceedings of the 2nd ACM/IEEE International Symposium on Networks-on-Chips (NOCS 2008) 7 - 11 April 2008, Newcastle upon Tyne, UK |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 211-212 |
ISBN (Print) | 978-0-7695-3098-7 |
DOIs | |
Publication status | Published - 2008 |
Event | 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2008), April 7-11, 2008, Newcastle upon Tyne, UK - Newcastle University, Newcastle upon Tyne, United Kingdom Duration: 7 Apr 2008 → 11 Apr 2008 http://async.org.uk/nocs2008/ |
Conference
Conference | 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2008), April 7-11, 2008, Newcastle upon Tyne, UK |
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Abbreviated title | NOCS 2008 |
Country/Territory | United Kingdom |
City | Newcastle upon Tyne |
Period | 7/04/08 → 11/04/08 |
Internet address |