Application specific instruction-set processor template for motion estimation in video applications.

H. Peters; R. Sethuraman; A. Beric; P. Meeuwissen; S. Balakrishnan; C.A. Alba Pinto; W. Kruijtzer; F. Ernst; G. Alkadi; J. Meerbergen, van; G. Haan, de

doi:10.1109/TCSVT.2005.844462

Application specific instruction-set processor template for motion estimation in video applications.

H. Peters, R. Sethuraman, A. Beric, P. Meeuwissen, S. Balakrishnan, C.A. Alba Pinto, W. Kruijtzer, F. Ernst, G. Alkadi, J. Meerbergen, van, G. Haan, de

Electronic Systems

Research output: Contribution to journal › Article › Academic › peer-review

29 Citations (Scopus)

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Abstract

The gap between application specific integrated circuits (ASICs) and general-purpose programmable processors in terms of performance, power, cost and flexibility is well known. Application specific instruction-set processors (ASIPs) bridge this gap. In this work, we demonstrate the key benefits of ASIPs for several video applications. One of the most compute- and memory-intensive functions in video processing is motion estimation (ME). The focus of this work is on the design of a ME template, which is useful for several video applications like video encoding, obstacle detection, picturerate up-conversion, 2-D-to-3-D video conversion, etc. An instruction-set suitable for performing a variety of ME functions is developed. The ASIP is based on a very long instruction word (VLIW) processor template and meets low-power and low-cost requirements still providing the flexibility needed for the application domain. The ME ASIP design consumes 27 mW and takes an area of 1.1 mm2 in 0.13 µm technology performing picturerate up-conversion, for standard definition (CCIR601) resolution at 50 frames per second.

Original language	English
Pages (from-to)	508-527
Number of pages	21
Journal	IEEE Transactions on Circuits and Systems for Video Technology
Volume	15
Issue number	4
DOIs	https://doi.org/10.1109/TCSVT.2005.844462
Publication status	Published - 2005

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Peters, H., Sethuraman, R., Beric, A., Meeuwissen, P., Balakrishnan, S., Alba Pinto, C. A., Kruijtzer, W., Ernst, F., Alkadi, G., Meerbergen, van, J., & Haan, de, G. (2005). Application specific instruction-set processor template for motion estimation in video applications. IEEE Transactions on Circuits and Systems for Video Technology, 15(4), 508-527. https://doi.org/10.1109/TCSVT.2005.844462

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title = "Application specific instruction-set processor template for motion estimation in video applications.",

abstract = "The gap between application specific integrated circuits (ASICs) and general-purpose programmable processors in terms of performance, power, cost and flexibility is well known. Application specific instruction-set processors (ASIPs) bridge this gap. In this work, we demonstrate the key benefits of ASIPs for several video applications. One of the most compute- and memory-intensive functions in video processing is motion estimation (ME). The focus of this work is on the design of a ME template, which is useful for several video applications like video encoding, obstacle detection, picturerate up-conversion, 2-D-to-3-D video conversion, etc. An instruction-set suitable for performing a variety of ME functions is developed. The ASIP is based on a very long instruction word (VLIW) processor template and meets low-power and low-cost requirements still providing the flexibility needed for the application domain. The ME ASIP design consumes 27 mW and takes an area of 1.1 mm2 in 0.13 µm technology performing picturerate up-conversion, for standard definition (CCIR601) resolution at 50 frames per second.",

author = "H. Peters and R. Sethuraman and A. Beric and P. Meeuwissen and S. Balakrishnan and {Alba Pinto}, C.A. and W. Kruijtzer and F. Ernst and G. Alkadi and {Meerbergen, van}, J. and {Haan, de}, G.",

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Peters, H, Sethuraman, R, Beric, A, Meeuwissen, P, Balakrishnan, S, Alba Pinto, CA, Kruijtzer, W, Ernst, F, Alkadi, G, Meerbergen, van, J & Haan, de, G 2005, 'Application specific instruction-set processor template for motion estimation in video applications.', IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 4, pp. 508-527. https://doi.org/10.1109/TCSVT.2005.844462

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AU - Peters, H.

AU - Sethuraman, R.

AU - Beric, A.

AU - Meeuwissen, P.

AU - Balakrishnan, S.

AU - Alba Pinto, C.A.

AU - Kruijtzer, W.

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AU - Alkadi, G.

AU - Meerbergen, van, J.

AU - Haan, de, G.

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N2 - The gap between application specific integrated circuits (ASICs) and general-purpose programmable processors in terms of performance, power, cost and flexibility is well known. Application specific instruction-set processors (ASIPs) bridge this gap. In this work, we demonstrate the key benefits of ASIPs for several video applications. One of the most compute- and memory-intensive functions in video processing is motion estimation (ME). The focus of this work is on the design of a ME template, which is useful for several video applications like video encoding, obstacle detection, picturerate up-conversion, 2-D-to-3-D video conversion, etc. An instruction-set suitable for performing a variety of ME functions is developed. The ASIP is based on a very long instruction word (VLIW) processor template and meets low-power and low-cost requirements still providing the flexibility needed for the application domain. The ME ASIP design consumes 27 mW and takes an area of 1.1 mm2 in 0.13 µm technology performing picturerate up-conversion, for standard definition (CCIR601) resolution at 50 frames per second.

AB - The gap between application specific integrated circuits (ASICs) and general-purpose programmable processors in terms of performance, power, cost and flexibility is well known. Application specific instruction-set processors (ASIPs) bridge this gap. In this work, we demonstrate the key benefits of ASIPs for several video applications. One of the most compute- and memory-intensive functions in video processing is motion estimation (ME). The focus of this work is on the design of a ME template, which is useful for several video applications like video encoding, obstacle detection, picturerate up-conversion, 2-D-to-3-D video conversion, etc. An instruction-set suitable for performing a variety of ME functions is developed. The ASIP is based on a very long instruction word (VLIW) processor template and meets low-power and low-cost requirements still providing the flexibility needed for the application domain. The ME ASIP design consumes 27 mW and takes an area of 1.1 mm2 in 0.13 µm technology performing picturerate up-conversion, for standard definition (CCIR601) resolution at 50 frames per second.

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JO - IEEE Transactions on Circuits and Systems for Video Technology

JF - IEEE Transactions on Circuits and Systems for Video Technology

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Application specific instruction-set processor template for motion estimation in video applications.

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