Apparatus and method for chip-scale package with capacitors as bumps

H.J. Bergveld (Inventor), J.W. Weekamp (Inventor), E.C.E. Grunsven, van (Inventor)

Research output: PatentPatent publication

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A method and apparatus relating to chip-scale packaging is provided. According to an embodiment of the invention electrical solder bump interconnection between an integrated circuit package and a substrate is replaced by the placement and attachment of discrete SMD components between pads on the integrated circuit and substrate. Said substrate being for example a low-temperature co-fired ceramic such as alumina or a PCB such as FR4. Accordingly discrete SMD capacitors, inductors etc can be packaged with the system design goals of minimizing board real-estate, enhancing performance, and cost addressed in a novel manner without requiring substantial development of new processes by manufacturers. The embodiments of the invention minimizing the parasitic series impedance of decoupling capacitor connections for example whilst allowing a small-form-factor System-in-Package to be realized.
Original languageEnglish
Patent numberWO2009083890
Publication statusPublished - 9 Jul 2009


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