Apparatus and method for chip-scale package with capacitors as bumps

H.J. Bergveld; J.W. Weekamp; E.C.E. Grunsven, van

Apparatus and method for chip-scale package with capacitors as bumps

H.J. Bergveld (Inventor), J.W. Weekamp (Inventor), E.C.E. Grunsven, van (Inventor)

Control Systems

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Abstract

A method and apparatus relating to chip-scale packaging is provided. According to an embodiment of the invention electrical solder bump interconnection between an integrated circuit package and a substrate is replaced by the placement and attachment of discrete SMD components between pads on the integrated circuit and substrate. Said substrate being for example a low-temperature co-fired ceramic such as alumina or a PCB such as FR4. Accordingly discrete SMD capacitors, inductors etc can be packaged with the system design goals of minimizing board real-estate, enhancing performance, and cost addressed in a novel manner without requiring substantial development of new processes by manufacturers. The embodiments of the invention minimizing the parasitic series impedance of decoupling capacitor connections for example whilst allowing a small-form-factor System-in-Package to be realized.

Original language	English
Patent number	WO2009083890
Publication status	Published - 9 Jul 2009

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abstract = "A method and apparatus relating to chip-scale packaging is provided. According to an embodiment of the invention electrical solder bump interconnection between an integrated circuit package and a substrate is replaced by the placement and attachment of discrete SMD components between pads on the integrated circuit and substrate. Said substrate being for example a low-temperature co-fired ceramic such as alumina or a PCB such as FR4. Accordingly discrete SMD capacitors, inductors etc can be packaged with the system design goals of minimizing board real-estate, enhancing performance, and cost addressed in a novel manner without requiring substantial development of new processes by manufacturers. The embodiments of the invention minimizing the parasitic series impedance of decoupling capacitor connections for example whilst allowing a small-form-factor System-in-Package to be realized.",

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T1 - Apparatus and method for chip-scale package with capacitors as bumps

AU - Bergveld, H.J.

AU - Weekamp, J.W.

AU - Grunsven, van, E.C.E.

PY - 2009/7/9

Y1 - 2009/7/9

N2 - A method and apparatus relating to chip-scale packaging is provided. According to an embodiment of the invention electrical solder bump interconnection between an integrated circuit package and a substrate is replaced by the placement and attachment of discrete SMD components between pads on the integrated circuit and substrate. Said substrate being for example a low-temperature co-fired ceramic such as alumina or a PCB such as FR4. Accordingly discrete SMD capacitors, inductors etc can be packaged with the system design goals of minimizing board real-estate, enhancing performance, and cost addressed in a novel manner without requiring substantial development of new processes by manufacturers. The embodiments of the invention minimizing the parasitic series impedance of decoupling capacitor connections for example whilst allowing a small-form-factor System-in-Package to be realized.

AB - A method and apparatus relating to chip-scale packaging is provided. According to an embodiment of the invention electrical solder bump interconnection between an integrated circuit package and a substrate is replaced by the placement and attachment of discrete SMD components between pads on the integrated circuit and substrate. Said substrate being for example a low-temperature co-fired ceramic such as alumina or a PCB such as FR4. Accordingly discrete SMD capacitors, inductors etc can be packaged with the system design goals of minimizing board real-estate, enhancing performance, and cost addressed in a novel manner without requiring substantial development of new processes by manufacturers. The embodiments of the invention minimizing the parasitic series impedance of decoupling capacitor connections for example whilst allowing a small-form-factor System-in-Package to be realized.

UR - http://v3.espacenet.com/publicationDetails/biblio?DB=EPODOC&adjacent=true&locale=nl_nl&FT=D&date=20090709&CC=WO&NR=2009083890A1&KC=A1

M3 - Patent publication

M1 - WO2009083890

ER -

Apparatus and method for chip-scale package with capacitors as bumps

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