Analytic processor model for fast design-space exploration

R. Jongerius; G. Mariani; A. Anghel; G. Dittmann; E. Vermij; H. Corporaal

doi:10.1109/ICCD.2015.7357136

Analytic processor model for fast design-space exploration

R. Jongerius, G. Mariani, A. Anghel, G. Dittmann, E. Vermij, H. Corporaal

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

12 Citations (Scopus)

1 Downloads (Pure)

Abstract

In this paper, we propose an analytic model that takes as inputs a) a parametric microarchitecture-independent characterization of the target workload, and b) a hardware configuration of the core and the memory hierarchy, and returns as output an estimation of processor-core performance. To validate our technique, we compare our performance estimates with measurements on an Intel® Xeon® system. The average error increases from 21% for a state-of-The-Art simulator to 25% for our model, but we achieve a speedup of several orders of magnitude. Thus, the model enables fast designspace exploration and represents a first step towards an analytic exascale system model.

Original language	English
Title of host publication	Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	411-414
Number of pages	4
ISBN (Electronic)	978-1-4673-7165-0
DOIs	https://doi.org/10.1109/ICCD.2015.7357136
Publication status	Published - 14 Dec 2015
Event	33rd IEEE International Conference on Computer Design (ICCD 2015) - New York City, United States Duration: 18 Oct 2015 → 21 Oct 2015 Conference number: 33

Conference

Conference	33rd IEEE International Conference on Computer Design (ICCD 2015)
Abbreviated title	ICCD 2015
Country/Territory	United States
City	New York City
Period	18/10/15 → 21/10/15

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10.1109/ICCD.2015.7357136

Cite this

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title = "Analytic processor model for fast design-space exploration",

abstract = "In this paper, we propose an analytic model that takes as inputs a) a parametric microarchitecture-independent characterization of the target workload, and b) a hardware configuration of the core and the memory hierarchy, and returns as output an estimation of processor-core performance. To validate our technique, we compare our performance estimates with measurements on an Intel{\textregistered} Xeon{\textregistered} system. The average error increases from 21% for a state-of-The-Art simulator to 25% for our model, but we achieve a speedup of several orders of magnitude. Thus, the model enables fast designspace exploration and represents a first step towards an analytic exascale system model.",

author = "R. Jongerius and G. Mariani and A. Anghel and G. Dittmann and E. Vermij and H. Corporaal",

year = "2015",

month = dec,

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doi = "10.1109/ICCD.2015.7357136",

language = "English",

pages = "411--414",

booktitle = "Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "33rd IEEE International Conference on Computer Design (ICCD 2015), ICCD 2015 ; Conference date: 18-10-2015 Through 21-10-2015",

}

Jongerius, R, Mariani, G, Anghel, A, Dittmann, G, Vermij, E & Corporaal, H 2015, Analytic processor model for fast design-space exploration. in Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015., 7357136, Institute of Electrical and Electronics Engineers, Piscataway, pp. 411-414, 33rd IEEE International Conference on Computer Design (ICCD 2015), New York City, New York, United States, 18/10/15. https://doi.org/10.1109/ICCD.2015.7357136

Analytic processor model for fast design-space exploration. / Jongerius, R.; Mariani, G.; Anghel, A. et al.
Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015. Piscataway: Institute of Electrical and Electronics Engineers, 2015. p. 411-414 7357136.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Analytic processor model for fast design-space exploration

AU - Jongerius, R.

AU - Mariani, G.

AU - Anghel, A.

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AU - Vermij, E.

AU - Corporaal, H.

N1 - Conference code: 33

PY - 2015/12/14

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N2 - In this paper, we propose an analytic model that takes as inputs a) a parametric microarchitecture-independent characterization of the target workload, and b) a hardware configuration of the core and the memory hierarchy, and returns as output an estimation of processor-core performance. To validate our technique, we compare our performance estimates with measurements on an Intel® Xeon® system. The average error increases from 21% for a state-of-The-Art simulator to 25% for our model, but we achieve a speedup of several orders of magnitude. Thus, the model enables fast designspace exploration and represents a first step towards an analytic exascale system model.

AB - In this paper, we propose an analytic model that takes as inputs a) a parametric microarchitecture-independent characterization of the target workload, and b) a hardware configuration of the core and the memory hierarchy, and returns as output an estimation of processor-core performance. To validate our technique, we compare our performance estimates with measurements on an Intel® Xeon® system. The average error increases from 21% for a state-of-The-Art simulator to 25% for our model, but we achieve a speedup of several orders of magnitude. Thus, the model enables fast designspace exploration and represents a first step towards an analytic exascale system model.

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BT - Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 33rd IEEE International Conference on Computer Design (ICCD 2015)

Y2 - 18 October 2015 through 21 October 2015

ER -

Analytic processor model for fast design-space exploration

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