Analytic processor model for fast design-space exploration

R. Jongerius, G. Mariani, A. Anghel, G. Dittmann, E. Vermij, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

9 Citations (Scopus)
1 Downloads (Pure)

Abstract

In this paper, we propose an analytic model that takes as inputs a) a parametric microarchitecture-independent characterization of the target workload, and b) a hardware configuration of the core and the memory hierarchy, and returns as output an estimation of processor-core performance. To validate our technique, we compare our performance estimates with measurements on an Intel® Xeon® system. The average error increases from 21% for a state-of-The-Art simulator to 25% for our model, but we achieve a speedup of several orders of magnitude. Thus, the model enables fast designspace exploration and represents a first step towards an analytic exascale system model.

Original languageEnglish
Title of host publicationProceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages411-414
Number of pages4
ISBN (Electronic)978-1-4673-7165-0
DOIs
Publication statusPublished - 14 Dec 2015
Event33rd IEEE International Conference on Computer Design (ICCD 2015) - New York City, United States
Duration: 18 Oct 201521 Oct 2015
Conference number: 33

Conference

Conference33rd IEEE International Conference on Computer Design (ICCD 2015)
Abbreviated titleICCD 2015
Country/TerritoryUnited States
CityNew York City
Period18/10/1521/10/15

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