Analysis of Bernstein's factorization circuit

A.K. Lenstra, A. Shamir, J. Tomlinson, E. Tromer

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

17 Citations (Scopus)

Abstract

In [1], Bernstein proposed a circuit-based implementation of the matrix step of the number field sieve factorization algorithm. These circuits offer an asymptotic cost reduction under the measure "construction cost x run time". We evaluate the cost of these circuits, in agreement with [1], but argue that compared to previously known methods these circuits can factor integers that are 1.17 times larger, rather than 3.01 as claimed (and even this, only under the non-standard cost measure). We also propose an improved circuit design based on a new mesh routing logarith, and show that for factorization of 1024-bit integers the matrix step can, under an optimistic assumption about the matrix size, be completed within a day by a device that costs a few thousand dollars. We conclude that from a practical standpoint, the security of RSA relies exclusively on the hardness of the relation collection step of the number field sieve.
Original languageEnglish
Title of host publicationAdvances in Cryptology - ASIACRYPT 2002 (Proceedings 8th International Conference on the Theory and Application of Cryptology and Information Security, Queenstown, New Zealand, December 1-5, 2002)
EditorsY. Zheng
Place of PublicationBerlin
PublisherSpringer
Pages1-26
ISBN (Print)3-540-00171-9
DOIs
Publication statusPublished - 2002

Publication series

NameLecture Notes in Computer Science
Volume2501
ISSN (Print)0302-9743

Fingerprint Dive into the research topics of 'Analysis of Bernstein's factorization circuit'. Together they form a unique fingerprint.

Cite this